Datasheet
MSP430F6438, MSP430F6436
MSP430F6435, MSP430F6433
SLAS720C –AUGUST 2010–REVISED AUGUST 2013
www.ti.com
DESCRIPTION
The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in
3 µs (typical).
The MSP430F643x series are microcontroller configurations with an integrated 3.3-V LDO, a high-performance
12-bit analog-to-digital converter (ADC), comparator, two universal serial communication interfaces (USCIs), a
hardware multiplier, DMA, four 16-bit timers, a real-time clock module with alarm capabilities, an LCD driver, and
up to 74 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, and hand-held meters.
Table 1 summarizes the available family members.
Table 1. Family Members
(1)(2)
USCI
Flash SRAM ADC12_A DAC12_A Comp_B Package
Channel A: Channel B:
Device Timer_A
(3)
Timer_B
(4)
I/O
(KB) (KB) (Ch) (Ch) (Ch) Type
UART,
SPI, I
2
C
IrDA, SPI
12 ext, 100 PZ,
MSP430F6438 256 18 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6436 128 18 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6435 256 18 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6433 128 10 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at http://www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
http://www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
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