Datasheet

2.01.8
8
0
12
20
25
SystemFrequency-MHz
SupplyVoltage-V
ThenumberswithinthefieldsdenotethesupportedPMMCOREVxsettings.
2.2 2.4 3.6
0,1,2,30,1,20,10
1,2,3
1,2
1
2,3
3
2
16
MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Recommended Operating Conditions (continued)
MIN NOM MAX UNIT
C
VCORE
Capacitor at VCORE 470 nF
C
DVCC
/
Capacitor ratio of DVCC to VCORE 10
C
VCORE
PMMCOREVx = 0,
1.8 V ≤ V
CC
≤ 3.6 V 0 8.0
(default condition)
PMMCOREVx = 1,
0 12.0
Processor frequency (maximum MCLK frequency)
(4)(5)
2 V ≤ V
CC
≤ 3.6 V
f
SYSTEM
MHz
(see Figure 2)
PMMCOREVx = 2,
0 16.0
2.2 V ≤ V
CC
≤ 3.6 V
PMMCOREVx = 3,
0 20.0
2.4 V ≤ V
CC
≤ 3.6 V
f
SYSTEM_USB
Minimum processor frequency for USB operation 1.5 MHz
USB_wait Wait state cycles during USB operation 16 cycles
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Figure 2. Frequency vs Supply Voltage
46 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630