Datasheet

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
NO. I/O
(1)
DESCRIPTION
NAME
PZ ZQW
General-purpose digital I/O
P5.6/ADC12CLK/DMAE0 16 H1 I/O
Conversion clock output ADC (not available on F5632, F5631, F5630 devices)
DMA external trigger input
General-purpose digital I/O with port interrupt and mappable secondary function
P2.0/P2MAP0 17 G4 I/O
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
General-purpose digital I/O with port interrupt and mappable secondary function
P2.1/P2MAP1 18 H2 I/O
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and mappable secondary function
P2.2/P2MAP2 19 J1 I/O
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
General-purpose digital I/O with port interrupt and mappable secondary function
P2.3/P2MAP3 20 H4 I/O
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
General-purpose digital I/O with port interrupt and mappable secondary function
P2.4/P2MAP4 21 J2 I/O
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
General-purpose digital I/O with port interrupt and mappable secondary function
P2.5/P2MAP5 22 K1 I/O
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
General-purpose digital I/O with port interrupt and mappable secondary function
P2.6/P2MAP6 23 K2 I/O
Default mapping: no secondary function
General-purpose digital I/O with port interrupt and mappable secondary function
P2.7/P2MAP7 24 L2 I/O
Default mapping: no secondary function
DVCC1 25 L1 Digital power supply
DVSS1 26 M1 Digital ground supply
VCORE
(2)
27 M2 Regulated core power supply (internal use only, no external current loading)
P5.2 28 L3 I/O
General-purpose digital I/O
DVSS 29 M3 Digital ground supply
DNC 30 J4 Do not connect. It is strongly recommended to leave this terminal open.
P5.3 31 L4 I/O
General-purpose digital I/O
P5.4 32 M4 I/O
General-purpose digital I/O
P5.5 33 J5 I/O
General-purpose digital I/O
General-purpose digital I/O with port interrupt
P1.0/TA0CLK/ACLK 34 L5 I/O
Timer TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
P1.1/TA0.0 35 M5 I/O
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt
P1.2/TA0.1 36 J6 I/O
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
General-purpose digital I/O with port interrupt
P1.3/TA0.2 37 H6 I/O
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P1.4/TA0.3 38 M6 I/O
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C
VCORE
.
10 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630