Datasheet
Table Of Contents
- Features
- Description
- Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN
- Pin Designation – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN
- Functional Block Diagram – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGC MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
- Pin Designation – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGC
- Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
- Pin Designation – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
- Functional Block Diagram – MSP430F5514IRGC, MSP430F5513IRGC, MSP430F5514IZQE, MSP430F5513IZQE
- Pin Designation – MSP430F5514IRGC, MSP430F5513IRGC
- Pin Designation – MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE, MSP430F5514IZQE, MSP430F5513IZQE
- Pin Designation – MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
- Short-Form Description
- CPU
- Operating Modes
- Interrupt Vector Addresses
- Memory Organization
- Bootstrap Loader (BSL)
- JTAG Operation
- Flash Memory (Link to User's Guide)
- RAM Memory (Link to User's Guide)
- Peripherals
- Digital I/O (Link to User's Guide)
- Port Mapping Controller (Link to User's Guide)
- Oscillator and System Clock (Link to User's Guide)
- Power Management Module (PMM) (Link to User's Guide)
- Hardware Multiplier (Link to User's Guide)
- Real-Time Clock (RTC_A) (Link to User's Guide)
- Watchdog Timer (WDT_A) (Link to User's Guide)
- System Module (SYS) (Link to User's Guide)
- DMA Controller (Link to User's Guide)
- Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
- TA0 (Link to User's Guide)
- TA1 (Link to User's Guide)
- TA2 (Link to User's Guide)
- TB0 (Link to User's Guide)
- Comparator_B (Link to User's Guide)
- ADC12_A (Link to User's Guide)
- CRC16 (Link to User's Guide)
- REF Voltage Reference (Link to User's Guide)
- USB Universal Serial Bus (Link to User's Guide)
- Embedded Emulation Module (EEM) (Link to User's Guide)
- Peripheral File Map
- Absolute Maximum Ratings
- Thermal Packaging Characteristics
- Recommended Operating Conditions
- Electrical Characteristics
- Active Mode Supply Current Into VCC Excluding External Current
- Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- Schmitt-Trigger Inputs – General Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
- Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
- Leakage Current – General Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
- Outputs – General Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
- Outputs – General Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
- Output Frequency – General Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
- Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- Crystal Oscillator, XT1, Low-Frequency Mode
- Crystal Oscillator, XT2
- Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- Internal Reference, Low-Frequency Oscillator (REFO)
- DCO Frequency
- PMM, Brown-Out Reset (BOR)
- PMM, Core Voltage
- PMM, SVS High Side
- PMM, SVM High Side
- PMM, SVS Low Side
- PMM, SVM Low Side
- Wake-Up From Low-Power Modes and Reset
- Timer_A
- Timer_B
- USCI (UART Mode) Recommended Operating Conditions
- USCI (UART Mode)
- USCI (SPI Master Mode) Recommended Operating Conditions
- USCI (SPI Master Mode)
- USCI (SPI Slave Mode)
- USCI (I2C Mode)
- 12-Bit ADC, Power Supply and Input Range Conditions
- 12-Bit ADC, Timing Parameters
- 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
- 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
- 12-Bit ADC, Temperature Sensor and Built-In VMID
- REF, External Reference
- REF, Built-In Reference
- Comparator_B
- Ports PU.0 and PU.1
- USB Output Ports DP and DM
- USB Input Ports DP and DM
- USB-PWR (USB Power System)
- USB-PLL (USB Phase Locked Loop)
- Flash Memory
- JTAG and Spy-Bi-Wire Interface
- Input/Output Schematics
- Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
- Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
- Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
- Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
- Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
- Port P5, P5.2, Input/Output With Schmitt Trigger
- Port P5, P5.3, Input/Output With Schmitt Trigger
- Port P5, P5.6 to P5.7, Input/Output With Schmitt Trigger
- Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
- Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger
- Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
- Port P8, P8.0 to P8.2, Input/Output With Schmitt Trigger
- Port PU.0/DP, PU.1/DM, PUR USB Ports
- Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
- Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- Device Descriptors (TLV)
- Revision History

MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
www.ti.com
SLAS590L –MARCH 2009–REVISED MAY 2013
REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Positive external reference
V
eREF+
V
eREF+
> V
REF–
and V
eREF–
(2)
1.4 AV
CC
V
voltage input
Negative external reference
V
REF–
, V
eREF–
V
eREF+
> V
REF–
and V
eREF–
(3)
0 1.2 V
voltage input
(V
eREF+
– Differential external reference
V
eREF+
> V
REF–
and V
eREF–
(4)
1.4 AV
CC
V
V
REF-
or V
eREF-
) voltage input
1.4 V ≤ V
eREF+
≤ V
AVCC
,
V
eREF–
= 0 V, f
ADC12CLK
= 5 MHz,
2.2 V, 3 V -26 26 µA
ADC12SHTx = 1h,
Conversion rate 200 ksps
I
VeREF+,
I
VREF-,
Static input current
VeREF-
1.4 V ≤ V
eREF+
≤ V
AVCC
,
V
eREF–
= 0 V, f
ADC12CLK
= 5 MHz,
2.2 V, 3 V -1 1 µA
ADC12SHTx = 8h,
Conversion rate 20 ksps
Capacitance at V
VREF+
, V
VREF-
C
VREF+
, C
VREF-
(5)
10 µF
terminal
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance (C
i
) is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
REFVSEL = {2} for 2.5 V,
3 V 2.4625 2.50 2.5375
REFON = REFOUT = 1, I
VREF+
= 0 A
Positive built-in reference REFVSEL = {1} for 2.0 V,
V
REF+
3 V 1.9503 1.98 2.0097 V
voltage output REFON = REFOUT = 1, I
VREF+
= 0 A
REFVSEL = {0} for 1.5 V,
2.2 V, 3 V 1.4677 1.49 1.5124
REFON = REFOUT = 1, I
VREF+
= 0 A
REFVSEL = {0} for 1.5 V 2.2
AVCC minimum voltage,
AV
CC(min)
Positive built-in reference REFVSEL = {1} for 2.0 V 2.3 V
active
REFVSEL = {2} for 2.5 V 2.8
ADC12SR = 1
(4)
, REFON = 1, REFOUT = 0,
3 V 70 100 µA
REFBURST = 0
ADC12SR = 1
(4)
, REFON = 1, REFOUT = 1,
3 V 0.45 0.75 mA
REFBURST = 0
Operating supply current into
I
REF+
AVCC terminal
(2)(3)
ADC12SR = 0
(4)
, REFON = 1, REFOUT = 0,
3 V 210 310 µA
REFBURST = 0
ADC12SR = 0
(4)
, REFON = 1, REFOUT = 1,
3 V 0.95 1.7 mA
REFBURST = 0
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,
used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference
for the conversion and utilizes the smaller buffer.
(2) The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
(3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to I
REF+
with
REFON =1 and REFOUT = 0.
(4) For devices without the ADC12, the parametrics with ADC12SR = 0 are applicable.
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