Datasheet

MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590L –MARCH 2009–REVISED MAY 2013 www.ti.com
TB0 (Link to User's Guide)
TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 17. TB0 Signal Connections
INPUT PIN NUMBER OUTPUT PIN NUMBER
DEVICE MODULE MODULE DEVICE
MODULE
INPUT INPUT OUTPUT OUTPUT
RGC, YFF, RGC, YFF,
BLOCK
PN PN
SIGNAL SIGNAL SIGNAL SIGNAL
ZQE
(1)
ZQE
(1)
60-P7.7 TB0CLK TBCLK
ACLK
ACLK
(internal)
Timer NA NA
SMCLK
SMCLK
(internal)
60-P7.7 TB0CLK TBCLK
55-P5.6 TB0.0 CCI0A 55-P5.6
ADC12 ADC12
(internal)
(2)
(internal)
(2)
55-P5.6 TB0.0 CCI0B
ADC12SHSx = ADC12SHSx =
CCR0 TB0 TB0.0
{2} {2}
DV
SS
GND
DV
CC
V
CC
56-P5.7 TB0.1 CCI1A 56-P5.7
ADC12 (internal) ADC12 (internal)
CBOUT
CCI1B ADC12SHSx = ADC12SHSx =
(internal)
CCR1 TB1 TB0.1
{3} {3}
DV
SS
GND
DV
CC
V
CC
57-P7.4 TB0.2 CCI2A 57-P7.4
57-P7.4 TB0.2 CCI2B
CCR2 TB2 TB0.2
DV
SS
GND
DV
CC
V
CC
58-P7.5 TB0.3 CCI3A 58-P7.5
58-P7.5 TB0.3 CCI3B
CCR3 TB3 TB0.3
DV
SS
GND
DV
CC
V
CC
59-P7.6 TB0.4 CCI4A 59-P7.6
59-P7.6 TB0.4 CCI4B
CCR4 TB4 TB0.4
DV
SS
GND
DV
CC
V
CC
42-P3.5 TB0.5 CCI5A 42-P3.5
42-P3.5 TB0.5 CCI5B
CCR5 TB5 TB0.5
DV
SS
GND
DV
CC
V
CC
43-P3.6 TB0.6 CCI6A 43-P3.6
ACLK
CCI6B
(internal)
CCR6 TB6 TB0.6
DV
SS
GND
DV
CC
V
CC
(1) Timer functions are selectable through the port mapping controller.
(2) Only on devices with ADC
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MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513