Datasheet

Unified
Clock
System
32KB
24KB
16KB
8KB
Flash
4KB+2KB
RAM
MCLK
ACLK
SMCLK
I/O Ports
P1, P2
1×8 I/Os
1
Interrupt,
Wakeup
PA
1×9 I/Os
×1 I/Os
CPUXV2
and
Working
Registers
EEM
(S:3+1)
XIN
XOUT
JTAG,
SBW
Interface
PA PB PC
DMA
3 Channel
XT2IN
XT2OUT
Power
Management
LDO
SVM, SVS,
Brownout
SYS
Watchdog
Port Map
Control
(P4)
I/O Ports
P4
1
PB
1×8 I/Os
×8 I/Os
I/O Ports
P5, P6
1×6 I/Os
1
PC
1×10 I/Os
×4 I/Os
Full-Speed
USB
USB-PHY
USB-LDO
USB-PLL
MPY32
TA0
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
USCI1
A1: UART,
IrDA, SPI
B1: SPI, I2C
ADC10_A
200 ksps
8 Channels
(6 int, 2 ext)
Window
Comparator
10 Bit
DV
CC
DV
SS
AV
CC
AV
SS
P1.x P2.x P4.x
P5.x P6.x
DP,DM,PUR
RST/NMI
TA2
Timer_A
3 CC
Registers
REF
V
CORE
MAB
MDB
MSP430F5510, MSP430F5509, MSP430F5508, MSP430F5507
MSP430F5506, MSP430F5505, MSP430F5504, MSP430F5503
MSP430F5502, MSP430F5501, MSP430F5500
www.ti.com SLAS645I –JULY 2009–REVISED NOVEMBER 2013
Functional Block Diagram – MSP430F5507IRGZ, MSP430F5506IRGZ, MSP430F5505IRGZ,
MSP430F5504IRGZ, MSP430F5504IPT
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Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505
MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500