Datasheet

MSP430F5510, MSP430F5509, MSP430F5508, MSP430F5507
MSP430F5506, MSP430F5505, MSP430F5504, MSP430F5503
MSP430F5502, MSP430F5501, MSP430F5500
www.ti.com SLAS645I –JULY 2009–REVISED NOVEMBER 2013
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at V
CC
to V
SS
–0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE, VBUS, V18)
(2)
–0.3 V to V
CC
+ 0.3 V
Diode current at any device pin ±2 mA
Storage temperature range, T
stg
(3)
–55°C to 150°C
Maximum junction temperature, T
J
95°C
(1) Stresses beyond those listed under "absolute maximum ratings " may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics
(1)
PARAMETER VALUE UNIT
VQFN (RGC) 30
VQFN (RGZ) 28.6
θ
JA
Junction-to-ambient thermal resistance, still air
(2)
°C/W
LQFP (PT) 62.8
BGA (ZQE) 55.5
VQFN (RGC) 15.6
VQFN (RGZ) 14.4
θ
JC(TOP)
Junction-to-case (top) thermal resistance
(3)
°C/W
LQFP (PT) 18.2
BGA (ZQE) 21.2
VQFN(RGC) 1.6
VQFN (RGZ) 1.6
θ
JC(BOTTOM)
Junction-to-case (bottom) thermal resistance
(4)
°C/W
LQFP (PT) N/A
BGA (ZQE) N/A
VQFN (RGC) 8.9
VQFN (RGZ) 5.5
θ
JB
Junction-to-board thermal resistance
(5)
°C/W
LQFP (PT) 28.3
BGA (ZQE) 19.3
(1) N/A = not applicable
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
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Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505
MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500