Datasheet

MSP430F5510, MSP430F5509, MSP430F5508, MSP430F5507
MSP430F5506, MSP430F5505, MSP430F5504, MSP430F5503
MSP430F5502, MSP430F5501, MSP430F5500
www.ti.com SLAS645I –JULY 2009–REVISED NOVEMBER 2013
TB0 (Link to User's Guide)
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 16. TB0 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
RGC, ZQE
(1)
RGZ, PT
(1)
RGC, ZQE
(1)
RGZ, PT
(1)
SIGNAL SIGNAL SIGNAL SIGNAL
TB0CLK TBCLK
ACLK
ACLK
(internal)
Timer NA NA
SMCLK
SMCLK
(internal)
TB0CLK TBCLK
ADC10 ADC10
(internal)
(2)
(internal)
(2)
TB0.0 CCI0A
ADC10SHSx = ADC10SHSx =
{2} {2}
CCR0 TB0 TB0.0
TB0.0 CCI0B
DV
SS
GND
DV
CC
V
CC
ADC10 (internal) ADC10 (internal)
TB0.1 CCI1A ADC10SHSx = ADC10SHSx =
{3} {3}
CBOUT
CCR1 TB1 TB0.1
CCI1B
(internal)
DV
SS
GND
DV
CC
V
CC
TB0.2 CCI2A
TB0.2 CCI2B
CCR2 TB2 TB0.2
DV
SS
GND
DV
CC
V
CC
TB0.3 CCI3A
TB0.3 CCI3B
CCR3 TB3 TB0.3
DV
SS
GND
DV
CC
V
CC
TB0.4 CCI4A
TB0.4 CCI4B
CCR4 TB4 TB0.4
DV
SS
GND
DV
CC
V
CC
TB0.5 CCI5A
TB0.5 CCI5B
CCR5 TB5 TB0.5
DV
SS
GND
DV
CC
V
CC
TB0.6 CCI6A
ACLK
CCI6B
(internal)
CCR6 TB6 TB0.6
DV
SS
GND
DV
CC
V
CC
(1) Timer functions selectable via the port mapping controller.
(2) Only on devices with ADC.
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MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500