Datasheet

MSP430F5510, MSP430F5509, MSP430F5508, MSP430F5507
MSP430F5506, MSP430F5505, MSP430F5504, MSP430F5503
MSP430F5502, MSP430F5501, MSP430F5500
www.ti.com SLAS645I –JULY 2009–REVISED NOVEMBER 2013
Table 1. Family Members
(1)(2)
USCI
PROGRAM
SRAM ADC10_A Comp_B PACKAGE
CHANNEL A: CHANNEL B:
DEVICE MEMORY Timer_A
(4)
Timer_B
(5)
I/O
(KB)
(3)
(CH) (CH) TYPE
UART, LIN,
SPI, I
2
C
(KB)
IrDA, SPI
64 RGC,
2 2 10 ext, 2 int 8 47
80 ZQE
MSP430F5510 32 4 + 2 5, 3, 3 7
48 PT,
1 1 6 ext, 2 int 4 31
48 RGZ
64 RGC,
2 2 10 ext, 2 int 8 47
80 ZQE
MSP430F5509 24 4 + 2 5, 3, 3 7
48 PT,
1 1 6 ext, 2 int 4 31
48 RGZ,
64 RGC,
2 2 10 ext, 2 int 8 47
80 ZQE
MSP430F5508 16 4 + 2 5, 3, 3 7
48 PT,
1 1 6 ext, 2 int 4 31
48 RGZ,
MSP430F5507 32 4 + 2 5, 3, 3 7 1 1 6 ext, 2 int - 31 48 RGZ
MSP430F5506 24 4 + 2 5, 3, 3 7 1 1 6 ext, 2 int - 31 48 RGZ
MSP430F5505 16 4 + 2 5, 3, 3 7 1 1 6 ext, 2 int - 31 48 RGZ
48 PT,
MSP430F5504 8 4 + 2 5, 3, 3 7 1 1 6 ext, 2 int - 31
48 RGZ
MSP430F5503 32 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ
MSP430F5502 24 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ
MSP430F5501 16 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ
MSP430F5500 8 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) The additional 2KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
(4) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
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Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505
MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500