Datasheet
MSP430F5510, MSP430F5509, MSP430F5508, MSP430F5507
MSP430F5506, MSP430F5505, MSP430F5504, MSP430F5503
MSP430F5502, MSP430F5501, MSP430F5500
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SLAS645I –JULY 2009–REVISED NOVEMBER 2013
RAM Memory (Link to User's Guide)
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in Memory Organization.
• Each sector 0 to n can be completely disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
• For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
Digital I/O (Link to User's Guide)
There are up to six 8-bit I/O ports implemented: For 64-pin options, P1, P2, P4, P6, and are complete, P5 is
reduced to 6-bit I/O and P3 to 5-bit I/O. For 48-pin options, P6 is reduced to 4-bit I/O, P2 to 1-bit I/O, and P3 is
completely removed. Port PJ contains four individual I/O ports, common to all devices.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Drive strength on all ports is programmable.
• Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P6) or word-wise in pairs (PA through PC).
Port Mapping Controller (Link to User's Guide)
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4.
Table 9. Port Mapping, Mnemonics and Functions
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
PM_CBOUT0 - Comparator_B output
1
PM_TB0CLK TB0 clock input
PM_ADC10CLK - ADC10CLK
2
PM_DMAE0 DMAE0 input
PM_SVMOUT - SVM output
3
PM_TB0OUTH TB0 high impedance input TB0OUTH
4 PM_TB0CCR0A TB0 CCR0 capture input CCI0A TB0 CCR0 compare output Out0
5 PM_TB0CCR1A TB0 CCR1 capture input CCI1A TB0 CCR1 compare output Out1
6 PM_TB0CCR2A TB0 CCR2 capture input CCI2A TB0 CCR2 compare output Out2
7 PM_TB0CCR3A TB0 CCR3 capture input CCI3A TB0 CCR3 compare output Out3
8 PM_TB0CCR4A TB0 CCR4 capture input CCI4A TB0 CCR4 compare output Out4
9 PM_TB0CCR5A TB0 CCR5 capture input CCI5A TB0 CCR5 compare output Out5
10 PM_TB0CCR6A TB0 CCR6 capture input CCI6A TB0 CCR6 compare output Out6
PM_UCA1RXD USCI_A1 UART RXD (Direction controlled by USCI - input)
11
PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI)
PM_UCA1TXD USCI_A1 UART TXD (Direction controlled by USCI - output)
12
PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI)
PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI)
13
PM_UCB1STE USCI_B1 SPI slave transmit enable (direction controlled by USCI)
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Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505
MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500