Datasheet

MSP430F5510, MSP430F5509, MSP430F5508, MSP430F5507
MSP430F5506, MSP430F5505, MSP430F5504, MSP430F5503
MSP430F5502, MSP430F5501, MSP430F5500
www.ti.com SLAS645I –JULY 2009–REVISED NOVEMBER 2013
Table 2. Terminal Functions (continued)
TERMINAL
NO.
I/O
(1)
DESCRIPTION
NAME
RGZ,
RGC ZQE
PT
General-purpose digital I/O with reconfigurable port mapping secondary
P4.4/PM_UCA1TXD/ function
45 33 D7 I/O
PM_UCA1SIMO Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary
P4.5/PM_UCA1RXD/ function
46 34 C9 I/O
PM_UCA1SOMI Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary
P4.6/PM_NONE 47 35 C8 I/O function
Default mapping: no secondary function.
General-purpose digital I/O with reconfigurable port mapping secondary
P4.7/PM_NONE 48 36 C7 I/O function
Default mapping: no secondary function.
B8,
VSSU 49 37 USB PHY ground supply
B9
General-purpose digital I/O - controlled by USB control register
PU.0/DP 50 38 A9 I/O
USB data terminal DP
USB pullup resistor pin (open drain). The voltage level at the PUR pin is
PUR 51 39 B7 I/O used to invoke the default USB BSL. Recommended 1-MΩ resistor to
ground. See USB BSL for more information.
General-purpose digital I/O - controlled by USB control register
PU.1/DM 52 40 A8 I/O
USB data terminal DM
VBUS 53 41 A7 USB LDO input (connect to USB power source)
VUSB 54 42 A6 USB LDO output
V18 55 43 B6 USB regulated power (internal use only, no external current loading)
AVSS2 56 44 A5 Analog ground supply
General-purpose digital I/O
P5.2/XT2IN 57 45 B5 I/O
Input terminal for crystal oscillator XT2
General-purpose digital I/O
P5.3/XT2OUT 58 46 B4 I/O
Output terminal of crystal oscillator XT2
Test mode pin – select digital I/O on JTAG pins
TEST/SBWTCK 59 47 A4 I
Spy-By-Wire input clock
General-purpose digital I/O
PJ.0/TDO 60 23 C5 I/O
Test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK 61 24 C4 I/O
Test data input or test clock input
General-purpose digital I/O
PJ.2/TMS 62 25 A3 I/O
Test mode select
General-purpose digital I/O
PJ.3/TCK 63 26 B3 I/O
Test clock
Reset input active low
(3)
RST/NMI/SBWTDIO 64 48 A2 I/O Non-maskable interrupt input
Spy-By-Wire data input/output
General-purpose digital I/O
Comparator_B input CB0 (not available on F5507, F5506, F5505, F5504
P6.0/CB0/A0 1 1 A1 I/O devices)
Analog input A0 – ADC (not available on F5503, F5502, F5501, F5500
devices)
General-purpose digital I/O
Comparator_B input CB1 (not available on F5507, F5506, F5505, F5504
P6.1/CB1/A1 2 2 B2 I/O devices)
Analog input A1 – ADC (not available on F5503, F5502, F5501, F5500
devices)
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
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Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505
MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500