Datasheet

P10.0/UCB3STE/UCA3CLK
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
P10.3/UCB3CLK/UCA3STE
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXD/UCA3SOMI
P10.6
P10.7
Direction
0: Input
1: Output
P10SEL.x
1
0
P10DIR.x
P10IN.x
EN
Module X IN
1
0
Module X OUT
P10OUT.x
1
0
DV
SS
DV
CC
P10REN.x
Pad Logic
1
P10DS.x
0: Low drive
1: High drive
D
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
www.ti.com SLAS612D –AUGUST 2009–REVISED AUGUST 2013
Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
Table 56. Port P10 (P10.0 to P10.7) Pin Functions
CONTROL BITS/SIGNALS
(1)
PIN NAME (P10.x) x FUNCTION
P10DIR.x P10SEL.x
P10.0/UCB3STE/UCA3CLK 0 P10.0 (I/O) I: 0; O: 1 0
UCB3STE/UCA3CLK
(2) (3)
X 1
P10.1/UCB3SIMO/UCB3SDA 1 P10.1 (I/O) I: 0; O: 1 0
UCB3SIMO/UCB3SDA
(2) (4)
X 1
P10.2/UCB3SOMI/UCB3SCL 2 P10.2 (I/O) I: 0; O: 1 0
UCB3SOMI/UCB3SCL
(2) (4)
X 1
P10.3/UCB3CLK/UCA3STE 3 P10.3 (I/O) I: 0; O: 1 0
UCB3CLK/UCA3STE
(2)
X 1
P10.4/UCA3TXD/UCA3SIMO 4 P10.4 (I/O) I: 0; O: 1 0
UCA3TXD/UCA3SIMO
(2)
X 1
P10.5/UCA3RXD/UCA3SOMI 5 P10.5 (I/O) I: 0; O: 1 0
UCA3RXD/UCA3SOMI
(2)
X 1
P10.6 6 P10.6 (I/O) I: 0; O: 1 0
Reserved
(5)
X 1
P10.7 7 P10.7 (I/O) I: 0; O: 1 0
Reserved
(5)
x 1
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI_B3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(4) If the I2C functionality is selected, the output drives only the logical 0 to V
SS
level.
(5) The secondary functions on these pins are reserved for factory test purposes. Application should keep the P10SEL.x of these ports
cleared to prevent potential conflicts with the application.
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