Datasheet

STE
UCLK
CKPL =0
CKPL =1
SOMI
SIMO
t
SU,SI
t
HD,SI
t
VALID,SO
t
STE,LEAD
1/f
UCxCLK
t
LO/HI
t
LO/HI
t
STE,LAG
t
STE,DIS
t
STE,ACC
t
HD,SO
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
SLAS612D –AUGUST 2009–REVISED AUGUST 2013 www.ti.com
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1)
, Figure 14 and Figure 15)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
t
STE,LEAD
STE lead time, STE low to clock 2.2 V, 3 V 40 ns
t
STE,LAG
STE lag time, Last clock to STE high 2.2 V, 3 V 10 ns
t
STE,ACC
STE access time, STE low to SOMI data out 2.2 V, 3 V 40 ns
STE disable time, STE high to SOMI high
t
STE,DIS
2.2 V, 3 V 40 ns
impedance
2.2 V 20
t
SU,SI
SIMO input data setup time ns
3 V 15
2.2 V 10
t
HD,SI
SIMO input data hold time ns
3 V 10
2.2 V 62
UCLK edge to SOMI valid,
t
VALID,SO
SOMI output data valid time
(2)
ns
C
L
= 20 pF
3 V 50
2.2 V 0
t
HD,SO
SOMI output data hold time
(3)
C
L
= 20 pF ns
3 V 0
(1) f
UCxCLK
= 1/2×t
LO/HI
with t
LO/HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(USCI)
, t
SU,MI(Master)
+ t
VALID,SO(USCI)
).
For the master's parameters t
SU,MI(Master)
and t
VALID,MO(Master)
, see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 12 and Figure 13.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 12 and Figure 13.
Figure 14. SPI Slave Mode, CKPH = 0
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