Datasheet

MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435
MSP430F5419, MSP430F5418
SLAS612D –AUGUST 2009–REVISED AUGUST 2013 www.ti.com
USCI (UART Mode) Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
USCI
USCI input clock frequency External: UCLK f
SYSTEM
MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
f
BITCLK
1 MHz
(equals baud rate in MBaud)
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
2.2 V 50 600
t
τ
UART receive deglitch time
(1)
ns
3 V 50 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
USCI
USCI input clock frequency f
SYSTEM
MHz
Duty cycle = 50% ± 10%
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1)
, Figure 12 and Figure 13)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
SMCLK, ACLK
f
USCI
USCI input clock frequency f
SYSTEM
MHz
Duty cycle = 50% ± 10%
2.2 V 65
t
SU,MI
SOMI input data setup time ns
3 V 50
2.2 V 0
t
HD,MI
SOMI input data hold time ns
3 V 0
2.2 V 25
UCLK edge to SIMO valid,
t
VALID,MO
SIMO output data valid time
(2)
ns
C
L
= 20 pF
3 V 20
2.2 V
t
HD,MO
SIMO output data hold time
(3)
C
L
= 20 pF ns
3 V
(1) f
UCxCLK
= 1/2t
LO/HI
with tL
O/HI
≥ max(t
VALID,MO(USCI)
+ t
SU,SI(Slave)
, t
SU,MI(USCI)
+ t
VALID,SO(Slave)
).
For the slave's parameters t
SU,SI(Slave)
and t
VALID,SO(Slave)
refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 12 and Figure 13.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 12 and Figure 13.
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