Datasheet
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
From JTAG
1
0
PJDIR.x
PJIN.x
EN
1
0
From JTAG
PJOUT.x
1
0
DV
SS
DV
CC
PJREN.x
Pad Logic
1
PJDS.x
0: Low drive
1: High drive
D
DVSS
To JTAG
PJ.0/TDO
From JTAG
1
0
PJDIR.0
PJIN.0
EN
1
0
From JTAG
PJOUT.0
1
0
DV
SS
DV
CC
PJREN.0
Pad Logic
1
PJDS.0
0: Low drive
1: High drive
D
DVCC
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A
MSP430F5419A, MSP430F5418A
SLAS655D –JANUARY 2010–REVISED AUGUST 2013
www.ti.com
Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
90 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A
MSP430F5418A