Datasheet

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A
MSP430F5419A, MSP430F5418A
SLAS655D –JANUARY 2010–REVISED AUGUST 2013 www.ti.com
12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
AVCC and DVCC are connected together,
AV
CC
Analog supply voltage AVSS and DVSS are connected together, 2.2 3.6 V
V
(AVSS)
= V
(DVSS)
= 0 V
V
(Ax)
Analog input voltage range
(2)
All ADC12 analog input pins Ax 0 AV
CC
V
2.2 V 125 155
Operating supply current into
I
ADC12_A
f
ADC12CLK
= 5.0 MHz
(4)
µA
AVCC terminal
(3)
3 V 150 220
Only one terminal Ax can be selected at one
C
I
Input capacitance 2.2 V 20 25 pF
time
R
I
Input MUX ON resistance 0 V ≤ V
Ax
≤ AVCC 10 200 1900 Ω
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range V
R+
to V
R–
for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See REF, External Reference andREF, Built-In Reference.
(3) The internal reference supply current is not included in current consumption parameter I
ADC12_A
.
(4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0.
12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
For specified performance of ADC12 linearity
parameters using an external reference voltage or 0.45 4.8 5.0
AVCC as reference.
(1)
f
ADC12CLK
ADC conversion clock For specified performance of ADC12 linearity 2.2 V, 3 V MHz
0.45 2.4 4.0
parameters using the internal reference.
(2)
For specified performance of ADC12 linearity
0.45 2.4 2.7
parameters using the internal reference.
(3)
Internal ADC12
f
ADC12OSC
ADC12DIV = 0, f
ADC12CLK
= f
ADC12OSC
2.2 V, 3 V 4.2 4.8 5.4 MHz
oscillator
(4)
REFON = 0, Internal oscillator,
2.2 V, 3 V 2.4 3.1
ADC12OSC used for ADC conversion clock
t
CONVERT
Conversion time µs
External f
ADC12CLK
from ACLK, MCLK, or SMCLK,
(5)
ADC12SSEL ≠ 0
R
S
= 400 Ω, R
I
= 1000 Ω, C
I
= 20 pF,
t
Sample
Sampling time 2.2 V, 3 V 1000 ns
τ = [R
S
+ R
I
] × C
I
(6)
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with f
ADC12CLK
maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(5) 13 × ADC12DIV × 1/f
ADC12CLK
(6) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
t
Sample
= ln(2
n+1
) x (R
S
+ R
I
) × C
I
+ 800 ns, where n = ADC resolution = 12, R
S
= external source resistance
62 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A
MSP430F5418A