Datasheet
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A
MSP430F5419A, MSP430F5418A
www.ti.com
SLAS655D –JANUARY 2010–REVISED AUGUST 2013
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1)
, Figure 14 and Figure 15)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
1.8 V 11
PMMCOREV = 0 ns
3.0 V 8
t
STE,LEAD
STE lead time, STE low to clock
2.4 V 7
PMMCOREV = 3 ns
3.0 V 6
1.8 V 3
PMMCOREV = 0 ns
3.0 V 3
t
STE,LAG
STE lag time, Last clock to STE high
2.4 V 3
PMMCOREV = 3 ns
3.0 V 3
1.8 V 66
PMMCOREV = 0 ns
3.0 V 50
STE access time, STE low to SOMI data
t
STE,ACC
out
2.4 V 36
PMMCOREV = 3 ns
3.0 V 30
1.8 V 30
PMMCOREV = 0 ns
3.0 V 23
STE disable time, STE high to SOMI high
t
STE,DIS
impedance
2.4 V 16
PMMCOREV = 3 ns
3.0 V 13
1.8 V 5
PMMCOREV = 0 ns
3.0 V 5
t
SU,SI
SIMO input data setup time
2.4 V 2
PMMCOREV = 3 ns
3.0 V 2
1.8 V 5
PMMCOREV = 0 ns
3.0 V 5
t
HD,SI
SIMO input data hold time
2.4 V 5
PMMCOREV = 3 ns
3.0 V 5
1.8 V 76
UCLK edge to SOMI valid,
ns
C
L
= 20 pF, PMMCOREV = 0
3.0 V 60
t
VALID,SO
SOMI output data valid time
(2)
2.4 V 44
UCLK edge to SOMI valid,
ns
C
L
= 20 pF, PMMCOREV = 3
3.0 V 40
1.8 V 18
C
L
= 20 pF, PMMCOREV = 0 ns
3.0 V 12
t
HD,SO
SOMI output data hold time
(3)
2.4 V 10
C
L
= 20 pF, PMMCOREV = 3 ns
3.0 V 8
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(USCI)
, t
SU,MI(Master)
+ t
VALID,SO(USCI)
).
For the master's parameters t
SU,MI(Master)
and t
VALID,MO(Master)
refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 12 and Figure 13.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 12
and Figure 13.
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