Datasheet

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A
MSP430F5419A, MSP430F5418A
SLAS655D –JANUARY 2010–REVISED AUGUST 2013 www.ti.com
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK,
1.8 V/
f
TA
Timer_A input clock frequency External: TACLK, 25 MHz
3.0 V
Duty cycle = 50% ± 10%
All capture inputs, 1.8 V/
t
TA,cap
Timer_A capture timing 20 ns
Minimum pulse duration required for capture 3.0 V
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK,
1.8 V/
f
TB
Timer_B input clock frequency External: TBCLK, 25 MHz
3.0 V
Duty cycle = 50% ± 10%
All capture inputs, 1.8 V/
t
TB,cap
Timer_B capture timing 20 ns
Minimum pulse duration required for capture 3.0 V
USCI (UART Mode) Recommended Operating Conditions
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK,
f
USCI
USCI input clock frequency External: UCLK, f
SYSTEM
MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
f
BITCLK
1 MHz
(equals baud rate in MBaud)
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER V
CC
MIN TYP MAX UNIT
2.2 V 50 600
t
τ
UART receive deglitch time
(1)
ns
3 V 50 600
(1) Pulses on the UART receive input (UCxRX) that are shorter than the UART receive deglitch time are suppressed. To make sure that
pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.
56 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A
MSP430F5418A