Datasheet

Unified
Clock
System
256KB
192KB
128KB
Flash
16KB
RAM
MCLK
ACLK
SMCLK
I/OPorts
P1/P2
2×8I/Os
Interrupt
Capability
PA
1×16I/Os
CPUXV2
and
Working
Registers
EEM
(L:8+2)
XIN XOUT
JTAG/
Interface
SBW
PA PB PC PD
DMA
3Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
I/OPorts
P3/P4
2×8I/Os
PB
1×16I/Os
I/OPorts
P5/P6
2×8I/Os
PC
1×16I/Os
I/OPorts
P7/P8
2×8I/Os
PD
1×16I/Os
MPY32
TA0
Timer_A
5CC
Registers
TA1
Timer_A
3CC
Registers
TB0
Timer_B
7CC
Registers
RTC_A
CRC16
USCI0,1
UCSI_Ax:
UART,
IrDA,SPI
USCI_Bx:
SPI,I2C
DVCC
DVSS
AVCC
AVSS
P1.x P2.x
P3.x
P4.x
P5.x P6.x
P7.x
P8.x
RST/NMI
ADC12_A
200KSPS
16Channels
(14ext/2int)
Autoscan
12Bit
MAB
MDB
REF
Unified
Clock
System
256KB
192KB
128KB
Flash
16KB
RAM
MCLK
ACLK
SMCLK
I/OPorts
P1/P2
2×8I/Os
Interrupt
Capability
PA
1×16I/Os
CPUXV2
and
Working
Registers
EEM
(L:8+2)
XIN XOUT
JTAG/
Interface
SBW
PA PB PC PD
DMA
3Channel
XT2IN
XT OUT2
PE
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
PF
I/OPorts
P3/P4
2×8I/Os
PB
1×16I/Os
I/OPorts
P5/P6
2×8I/Os
PC
1×16I/Os
I/OPorts
P7/P8
2×8I/Os
PD
1×16I/Os
I/OPorts
P9/P10
2×8I/Os
PE
1×16I/Os
I/OPorts
P11
1×3I/Os
PF
1×3I/Os
MPY32
TA0
Timer_A
5CC
Registers
TA1
Timer_A
3CC
Registers
TB0
Timer_B
7CC
Registers
RTC_A
CRC16
USCI0,1,2,3
USCI_Ax:
UART,
IrDA,SPI
UCSI_Bx:
SPI,I2C
ADC12_A
200KSPS
16Channels
(14ext/2int)
Autoscan
12Bit
DVCC
DVSS
AVCC
AVSS
P1.x P2.x
P3.x
P4.x
P5.x P6.x
P7.x
P8.x P9.x P10.x
P11.x
RST/NMI
MAB
MDB
REF
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A
MSP430F5419A, MSP430F5418A
www.ti.com SLAS655D –JANUARY 2010–REVISED AUGUST 2013
Functional Block Diagram
MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ,
MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW
Functional Block Diagram
MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A
MSP430F5418A