Datasheet

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A
MSP430F5419A, MSP430F5418A
www.ti.com SLAS655D –JANUARY 2010–REVISED AUGUST 2013
Peripheral File Map
Table 12. Peripherals
OFFSET ADDRESS
MODULE NAME BASE ADDRESS
RANGE
Special Functions (see Table 13) 0100h 000h-01Fh
PMM (see Table 14) 0120h 000h-010h
Flash Control (see Table 15) 0140h 000h-00Fh
CRC16 (see Table 16) 0150h 000h-007h
RAM Control (see Table 17) 0158h 000h-001h
Watchdog (see Table 18) 015Ch 000h-001h
UCS (see Table 19) 0160h 000h-01Fh
SYS (see Table 20) 0180h 000h-01Fh
Shared Reference (see Table 21) 01B0h 000h-001h
Port P1, P2 (see Table 22) 0200h 000h-01Fh
Port P3, P4 (see Table 23) 0220h 000h-00Bh
Port P5, P6 (see Table 24) 0240h 000h-00Bh
Port P7, P8 (see Table 25) 0260h 000h-00Bh
Port P9, P10 (see Table 26) 0280h 000h-00Bh
Port P11 (see Table 27) 02A0h 000h-00Ah
Port PJ (see Table 28) 0320h 000h-01Fh
TA0 (see Table 29) 0340h 000h-02Eh
TA1 (see Table 30) 0380h 000h-02Eh
TB0 (see Table 31) 03C0h 000h-02Eh
Real Timer Clock (RTC_A) (see Table 32) 04A0h 000h-01Bh
32-Bit Hardware Multiplier (see Table 33) 04C0h 000h-02Fh
DMA General Control (see Table 34) 0500h 000h-00Fh
DMA Channel 0 (see Table 34) 0510h 000h-00Ah
DMA Channel 1 (see Table 34) 0520h 000h-00Ah
DMA Channel 2 (see Table 34) 0530h 000h-00Ah
USCI_A0 (see Table 35) 05C0h 000h-01Fh
USCI_B0 (see Table 36) 05E0h 000h-01Fh
USCI_A1 (see Table 37) 0600h 000h-01Fh
USCI_B1 (see Table 38) 0620h 000h-01Fh
USCI_A2 (see Table 39) 0640h 000h-01Fh
USCI_B2 (see Table 40) 0660h 000h-01Fh
USCI_A3 (see Table 41) 0680h 000h-01Fh
USCI_B3 (see Table 42) 06A0h 000h-01Fh
ADC12_A (see Table 43) 0700h 000h-03Eh
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MSP430F5418A