Datasheet
Table Of Contents
- Features
- Applications
- Description
- Development Tools Support
- Device and Development Tool Nomenclature
- Short-Form Description
- CPU
- Operating Modes
- Interrupt Vector Addresses
- Memory Organization
- Bootstrap Loader (BSL)
- JTAG Operation
- Flash Memory
- RAM Memory
- Peripherals
- Digital I/O
- Port Mapping Controller
- Oscillator and System Clock
- Power Management Module (PMM)
- Hardware Multiplier
- Real-Time Clock (RTC_A)
- Watchdog Timer (WDT_A)
- System Module (SYS)
- DMA Controller
- Universal Serial Communication Interface (USCI)
- TA0
- TA1
- TA2
- TB0
- Comparator_B
- ADC12_A
- CRC16
- REF Voltage Reference
- Embedded Emulation Module (EEM)
- Peripheral File Map
- Absolute Maximum Ratings
- Thermal Packaging Characteristics
- Recommended Operating Conditions
- Electrical Characteristics
- Active Mode Supply Current Into VCC Excluding External Current
- Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- Schmitt-Trigger Inputs – General Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
- Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
- Leakage Current – General Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
- Outputs – General Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
- Outputs – General Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
- Output Frequency – General Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
- Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- Crystal Oscillator, XT1, Low-Frequency Mode
- Crystal Oscillator, XT2
- Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- Internal Reference, Low-Frequency Oscillator (REFO)
- DCO Frequency
- PMM, Brown-Out Reset (BOR)
- PMM, Core Voltage
- PMM, SVS High Side
- PMM, SVM High Side
- PMM, SVS Low Side
- PMM, SVM Low Side
- Wake Up From Low Power Modes and Reset
- Timer_A
- Timer_B
- USCI (UART Mode) Recommended Operating Conditions
- USCI (UART Mode)
- USCI (SPI Master Mode) Recommended Operating Conditions
- USCI (SPI Master Mode)
- USCI (SPI Slave Mode)
- USCI (I2C Mode)
- 12-Bit ADC, Power Supply and Input Range Conditions
- 12-Bit ADC, Timing Parameters
- 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
- 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
- 12-Bit ADC, Temperature Sensor and Built-In VMID
- REF, External Reference
- REF, Built-In Reference
- Comparator B
- Flash Memory
- JTAG and Spy-Bi-Wire Interface
- Input/Output Schematics
- Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
- Port P2, P2.7, Input/Output With Schmitt Trigger
- Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger
- Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
- Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
- Port P5, P5.2, Input/Output With Schmitt Trigger
- Port P5, P5.3, Input/Output With Schmitt Trigger
- Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
- Port P5, P5.7, Input/Output With Schmitt Trigger
- Port P6, P6.1 to P6.5, Input/Output With Schmitt Trigger
- Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
- Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- Device Descriptors
- Revision History

MSP430F5342, MSP430F5341, MSP430F5340
www.ti.com
SLAS706E –JULY 2011–REVISED AUGUST 2013
Outputs – General Purpose I/O (Full Drive Strength)
(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)
(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
I
(OHmax)
= -3 mA
(1)
V
CC
– 0.25 V
CC
1.8 V
I
(OHmax)
= -10 mA
(2)
V
CC
– 0.60 V
CC
V
OH
High-level output voltage V
I
(OHmax)
= -5 mA
(1)
V
CC
– 0.25 V
CC
3 V
I
(OHmax)
= -15 mA
(2)
V
CC
– 0.60 V
CC
I
(OLmax)
= 3 mA
(1)
V
SS
V
SS
+ 0.25
1.8 V
I
(OLmax)
= 10 mA
(2)
V
SS
V
SS
+ 0.60
V
OL
Low-level output voltage V
I
(OLmax)
= 5 mA
(1)
V
SS
V
SS
+ 0.25
3 V
I
(OLmax)
= 15 mA
(2)
V
SS
V
SS
+ 0.60
(1) The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
Outputs – General Purpose I/O (Reduced Drive Strength)
(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)
(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
I
(OHmax)
= -1 mA
(2)
V
CC
– 0.25 V
CC
1.8 V
I
(OHmax)
= -3 mA
(3)
V
CC
– 0.60 V
CC
V
OH
High-level output voltage V
I
(OHmax)
= -2 mA
(2)
V
CC
– 0.25 V
CC
3 V
I
(OHmax)
= -6 mA
(3)
V
CC
– 0.60 V
CC
I
(OLmax)
= 1 mA
(2)
V
SS
V
SS
+ 0.25
1.8 V
I
(OLmax)
= 3 mA
(3)
V
SS
V
SS
+ 0.60
V
OL
Low-level output voltage V
I
(OLmax)
= 2 mA
(2)
V
SS
V
SS
+ 0.25
3 V
I
(OLmax)
= 6 mA
(3)
V
SS
V
SS
+ 0.60
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined, should not exceed ± 48 mA to hold the maximum voltage drop
specified.
(3) The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined, should not exceed ± 100 mA to hold the maximum voltage
drop specified.
Output Frequency – General Purpose I/O
(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)
(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
CC
= 1.8 V, PMMCOREVx = 0 16
f
Px.y
Port output frequency (with load)
(1) (2)
MHz
V
CC
= 3 V, PMMCOREVx = 3 25
ACLK, V
CC
= 1.8 V, PMMCOREVx = 0 16
SMCLK,
f
Port_CLK
Clock output frequency MHz
MCLK ,
V
CC
= 3 V, PMMCOREVx = 3 25
C
L
= 20 pF
(2)
(1) A resistive divider with 2 × R1 between V
CC
and V
SS
is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. C
L
= 20 pF is connected to the output to V
SS
.
(2) The output voltage reaches at least 10% and 90% V
CC
at the specified toggle frequency.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 41
Product Folder Links: MSP430F5342 MSP430F5341 MSP430F5340