Datasheet
Table Of Contents
- Features
- Applications
- Description
- Development Tools Support
- Device and Development Tool Nomenclature
- Short-Form Description
- CPU
- Operating Modes
- Interrupt Vector Addresses
- Memory Organization
- Bootstrap Loader (BSL)
- JTAG Operation
- Flash Memory
- RAM Memory
- Peripherals
- Digital I/O
- Port Mapping Controller
- Oscillator and System Clock
- Power Management Module (PMM)
- Hardware Multiplier
- Real-Time Clock (RTC_A)
- Watchdog Timer (WDT_A)
- System Module (SYS)
- DMA Controller
- Universal Serial Communication Interface (USCI)
- TA0
- TA1
- TA2
- TB0
- Comparator_B
- ADC12_A
- CRC16
- REF Voltage Reference
- Embedded Emulation Module (EEM)
- Peripheral File Map
- Absolute Maximum Ratings
- Thermal Packaging Characteristics
- Recommended Operating Conditions
- Electrical Characteristics
- Active Mode Supply Current Into VCC Excluding External Current
- Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- Schmitt-Trigger Inputs – General Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
- Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
- Leakage Current – General Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
- Outputs – General Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
- Outputs – General Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
- Output Frequency – General Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
- Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- Crystal Oscillator, XT1, Low-Frequency Mode
- Crystal Oscillator, XT2
- Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- Internal Reference, Low-Frequency Oscillator (REFO)
- DCO Frequency
- PMM, Brown-Out Reset (BOR)
- PMM, Core Voltage
- PMM, SVS High Side
- PMM, SVM High Side
- PMM, SVS Low Side
- PMM, SVM Low Side
- Wake Up From Low Power Modes and Reset
- Timer_A
- Timer_B
- USCI (UART Mode) Recommended Operating Conditions
- USCI (UART Mode)
- USCI (SPI Master Mode) Recommended Operating Conditions
- USCI (SPI Master Mode)
- USCI (SPI Slave Mode)
- USCI (I2C Mode)
- 12-Bit ADC, Power Supply and Input Range Conditions
- 12-Bit ADC, Timing Parameters
- 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
- 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
- 12-Bit ADC, Temperature Sensor and Built-In VMID
- REF, External Reference
- REF, Built-In Reference
- Comparator B
- Flash Memory
- JTAG and Spy-Bi-Wire Interface
- Input/Output Schematics
- Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
- Port P2, P2.7, Input/Output With Schmitt Trigger
- Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger
- Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
- Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
- Port P5, P5.2, Input/Output With Schmitt Trigger
- Port P5, P5.3, Input/Output With Schmitt Trigger
- Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
- Port P5, P5.7, Input/Output With Schmitt Trigger
- Port P6, P6.1 to P6.5, Input/Output With Schmitt Trigger
- Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
- Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- Device Descriptors
- Revision History
MSP430F5342, MSP430F5341, MSP430F5340
www.ti.com
SLAS706E –JULY 2011–REVISED AUGUST 2013
Table 3. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
0FFD0h 40
Reserved Reserved
(5)
⋮ ⋮
0FF80h 0, lowest
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
Memory Organization
Table 4. Memory Organization
(1)
MSP430F5340 MSP430F5341 MSP430F5342
Memory (flash) Total Size 64 KB 96 KB 128 KB
Main: interrupt vector 00FFFFh-00FF80h 00FFFFh-00FF80h 00FFFFh-00FF80h
N/A N/A 32 KB
Bank D
0243FFh-01C400h
N/A 32 KB 32 KB
Bank C
01C3FFh-014400h 01C3FFh-014400h
Main: code memory
32 KB 32 KB 32 KB
Bank B
0143FFh-00C400h 0143FFh-00C400h 0143FFh-00C400h
32 KB 32 KB 32 KB
Bank A
00C3FFh-004400h 00C3FFh-004400h 00C3FFh-004400h
Sector 3 N/A N/A 2 KB
0043FFh-003C00h
Sector 2 N/A 2 KB 2 KB
003BFFh-003400h 003BFFh-003400h
Sector 1 2 KB 2 KB 2 KB
RAM
0033FFh-002C00h 0033FFh-002C00h 0033FFh-002C00h
Sector 0 2 KB 2 KB 2 KB
002BFFh-002400h 002BFFh-002400h 002BFFh-002400h
Sector 7 2 KB 2 KB 2 KB
0023FFh-001C00h 0023FFh-001C00h 0023FFh-001C00h
Info A 128 B 128 B 128 B
0019FFh-001980h 0019FFh-001980h 0019FFh-001980h
Info B 128 B 128 B 128 B
00197Fh-001900h 00197Fh-001900h 00197Fh-001900h
Information memory (flash)
Info C 128 B 128 B 128 B
0018FFh-001880h 0018FFh-001880h 0018FFh-001880h
Info D 128 B 128 B 128 B
00187Fh-001800h 00187Fh-001800h 00187Fh-001800h
BSL 3 512 B 512 B 512 B
0017FFh-001600h 0017FFh-001600h 0017FFh-001600h
BSL 2 512 B 512 B 512 B
0015FFh-001400h 0015FFh-001400h 0015FFh-001400h
Bootstrap loader (BSL)
memory (flash)
BSL 1 512 B 512 B 512 B
0013FFh-001200h 0013FFh-001200h 0013FFh-001200h
BSL 0 512 B 512 B 512 B
0011FFh-001000h 0011FFh-001000h 0011FFh-001000h
Size 4 KB 4 KB 4 KB
Peripherals
000FFFh-0h 000FFFh-0h 000FFFh-0h
(1) N/A = Not available
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