Datasheet

MSP430F5342, MSP430F5341, MSP430F5340
www.ti.com SLAS706E –JULY 2011–REVISED AUGUST 2013
Wake Up From Low Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
MCLK
≥ 4.0 MHz 3.5 7.5
Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n
t
WAKE-UP-FAST
LPM3, or LPM4 to active (where n = 0, 1, 2, or 3), µs
1.0 MHz < f
MCLK
4.5 9
mode
(1)
SVSLFP = 1
< 4.0 MHz
Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n
t
WAKE-UP-SLOW
LPM3 or LPM4 to active (where n = 0, 1, 2, or 3), 150 165 µs
mode
(2)
SVSLFP = 0
Wake-up time from LPM4.5 to
t
WAKE-UP-LPM5
2 3 ms
active mode
(3)
Wake-up time from RST or
t
WAKE-UP-RESET
2 3 ms
BOR event to active mode
(3)
(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVS
L
) and low side monitor (SVM
L
). Fastest wakeup times are possible with SVS
L
and SVM
L
in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVS
L
and SVM
L
while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVS
L
) and low side monitor (SVM
L
). In this case, the SVS
L
and SVM
L
are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVS
L
and SVM
L
while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208).
(3) This value represents the time from the wakeup event to the reset vector execution.
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK,
f
TA
Timer_A input clock frequency External: TACLK, 1.8 V, 3 V 25 MHz
Duty cycle = 50% ± 10%
All capture inputs, minimum pulse
t
TA,cap
Timer_A capture timing 1.8 V, 3 V 20 ns
duration required for capture
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK,
f
TB
Timer_B input clock frequency External: TBCLK, 1.8 V, 3 V 25 MHz
Duty cycle = 50% ± 10%
All capture inputs, minimum pulse
t
TB,cap
Timer_B capture timing 1.8 V, 3 V 20 ns
duration required for capture
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