Datasheet

2.01.8
8
0
12
20
25
SystemFrequency-MHz
SupplyVoltage-V
ThenumberswithinthefieldsdenotethesupportedPMMCOREVxsettings.
2.2 2.4 3.6
0,1,2,30,1,20,10
1,2,3
1,2
1
2,3
3
2
MSP430F5342, MSP430F5341, MSP430F5340
www.ti.com SLAS706E –JULY 2011–REVISED AUGUST 2013
Recommended Operating Conditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25°C (unless otherwise noted)
MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6 V
PMMCOREVx = 0, 1 2.0 3.6 V
Supply voltage during program execution and flash
V
CC
programming (AVCCx = DVCCx = V
CC
)
(1)(2)
PMMCOREVx = 0, 1, 2 2.2 3.6 V
PMMCOREVx = 0, 1, 2, 3 2.4 3.6 V
V
SS
Supply voltage (AVSSx = DVSSx = V
SS
) 0 V
T
A
Operating free-air temperature -40 85 °C
T
J
Operating junction temperature -40 85 °C
C
VCORE
Recommended capacitor at VCORE 470 nF
C
DVCC
/
Capacitor ratio of DVCC to VCORE 10
C
VCORE
PMMCOREVx = 0,
1.8 V ≤ V
CC
≤ 3.6 V 0 8.0
(default condition)
PMMCOREVx = 1,
0 12.0
Processor frequency (maximum MCLK frequency)
(3)
2.0 V ≤ V
CC
≤ 3.6 V
f
SYSTEM
MHz
(see Figure 2)
PMMCOREVx = 2,
0 20.0
2.2 V ≤ V
CC
≤ 3.6 V
PMMCOREVx = 3,
0 25.0
2.4 V ≤ V
CC
≤ 3.6 V
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(3) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Figure 2. Maximum System Frequency
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