Datasheet
Table Of Contents
- Features
- Applications
- Description
- Development Tools Support
- Device and Development Tool Nomenclature
- Short-Form Description
- CPU
- Operating Modes
- Interrupt Vector Addresses
- Memory Organization
- Bootstrap Loader (BSL)
- JTAG Operation
- Flash Memory
- RAM Memory
- Peripherals
- Digital I/O
- Port Mapping Controller
- Oscillator and System Clock
- Power Management Module (PMM)
- Hardware Multiplier
- Real-Time Clock (RTC_A)
- Watchdog Timer (WDT_A)
- System Module (SYS)
- DMA Controller
- Universal Serial Communication Interface (USCI)
- TA0
- TA1
- TA2
- TB0
- Comparator_B
- ADC12_A
- CRC16
- REF Voltage Reference
- Embedded Emulation Module (EEM)
- Peripheral File Map
- Absolute Maximum Ratings
- Thermal Packaging Characteristics
- Recommended Operating Conditions
- Electrical Characteristics
- Active Mode Supply Current Into VCC Excluding External Current
- Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- Schmitt-Trigger Inputs – General Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
- Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
- Leakage Current – General Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
- Outputs – General Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
- Outputs – General Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
- Output Frequency – General Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
- Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- Crystal Oscillator, XT1, Low-Frequency Mode
- Crystal Oscillator, XT2
- Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- Internal Reference, Low-Frequency Oscillator (REFO)
- DCO Frequency
- PMM, Brown-Out Reset (BOR)
- PMM, Core Voltage
- PMM, SVS High Side
- PMM, SVM High Side
- PMM, SVS Low Side
- PMM, SVM Low Side
- Wake Up From Low Power Modes and Reset
- Timer_A
- Timer_B
- USCI (UART Mode) Recommended Operating Conditions
- USCI (UART Mode)
- USCI (SPI Master Mode) Recommended Operating Conditions
- USCI (SPI Master Mode)
- USCI (SPI Slave Mode)
- USCI (I2C Mode)
- 12-Bit ADC, Power Supply and Input Range Conditions
- 12-Bit ADC, Timing Parameters
- 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
- 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
- 12-Bit ADC, Temperature Sensor and Built-In VMID
- REF, External Reference
- REF, Built-In Reference
- Comparator B
- Flash Memory
- JTAG and Spy-Bi-Wire Interface
- Input/Output Schematics
- Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
- Port P2, P2.7, Input/Output With Schmitt Trigger
- Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger
- Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
- Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
- Port P5, P5.2, Input/Output With Schmitt Trigger
- Port P5, P5.3, Input/Output With Schmitt Trigger
- Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
- Port P5, P5.7, Input/Output With Schmitt Trigger
- Port P6, P6.1 to P6.5, Input/Output With Schmitt Trigger
- Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
- Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- Device Descriptors
- Revision History
MSP430F5342, MSP430F5341, MSP430F5340
SLAS706E –JULY 2011–REVISED AUGUST 2013
www.ti.com
Peripheral File Map
Table 16. Peripherals
OFFSET ADDRESS
MODULE NAME BASE ADDRESS
RANGE
Special Functions (see Table 17) 0100h 000h-01Fh
PMM (see Table 18) 0120h 000h-010h
Flash Control (see Table 19) 0140h 000h-00Fh
CRC16 (see Table 20) 0150h 000h-007h
RAM Control (see Table 21) 0158h 000h-001h
Watchdog (see Table 22) 015Ch 000h-001h
UCS (see Table 23) 0160h 000h-01Fh
SYS (see Table 24) 0180h 000h-01Fh
Shared Reference (see Table 25) 01B0h 000h-001h
Port Mapping Control (see Table 26) 01C0h 000h-002h
Port Mapping Port P4 (see Table 26) 01E0h 000h-007h
Port P1 and P2 (see Table 27) 0200h 000h-01Fh
Port P3 and P4 (see Table 28) 0220h 000h-00Bh
Port P5 and P6 (see Table 29) 0240h 000h-00Bh
Port PJ (see Table 30) 0320h 000h-01Fh
TA0 (see Table 31) 0340h 000h-02Eh
TA1 (see Table 32) 0380h 000h-02Eh
TB0 (see Table 33) 03C0h 000h-02Eh
TA2 (see Table 34) 0400h 000h-02Eh
Real-Time Clock (RTC_A) (see Table 35) 04A0h 000h-01Bh
32-Bit Hardware Multiplier (see Table 36) 04C0h 000h-02Fh
DMA General Control (see Table 37) 0500h 000h-00Fh
DMA Channel 0 (see Table 37) 0510h 000h-00Ah
DMA Channel 1 (see Table 37) 0520h 000h-00Ah
DMA Channel 2 (see Table 37) 0530h 000h-00Ah
USCI_A0 (see Table 38) 05C0h 000h-01Fh
USCI_B0 (see Table 39) 05E0h 000h-01Fh
USCI_A1 (see Table 40) 0600h 000h-01Fh
USCI_B1 (see Table 41) 0620h 000h-01Fh
ADC12_A (see Table 42) 0700h 000h-03Eh
Comparator_B (see Table 43) 08C0h 000h-00Fh
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