Datasheet

MSP430F5342, MSP430F5341, MSP430F5340
SLAS706E –JULY 2011–REVISED AUGUST 2013 www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices that feature
different sets of peripherals targeted for various applications. The architecture, combined with extensive low-
power modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active
mode in 3.5 µs (typical).
The MSP430F534x are microcontroller configurations with four 16-bit timers, a high-performance 12-bit analog-
to-digital converter (ADC), two universal serial communication interfaces (USCIs), a hardware multiplier, DMA, a
real-time clock module with alarm capabilities, and 38 I/O pins.
Typical applications include analog and digital sensor systems, data loggers, and various general-purpose
applications.
Table 1 summarizes the available family members.
Table 1. Family Members
(1)(2)
USCI
Flash SRAM ADC12_A Comp_B Package
Channel A: Channel B:
Device Timer_A
(3)
Timer_B
(4)
I/O
(KB) (KB) (Ch) (Ch) Type
UART, IrDA,
SPI, I
2
C
SPI
MSP430F5342 128 10 5, 3
(5)
, 3
(6)
7 2 2 7 ext, 2 int 5 38 48 RGZ
MSP430F5341 96 8 5, 3
(5)
, 3
(6)
7 2 2 7 ext, 2 int 5 38 48 RGZ
MSP430F5340 64 6 5, 3
(5)
, 3
(6)
7 2 2 7 ext, 2 int 5 38 48 RGZ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) Only one PWM output and one external capture input available at pin.
(6) No PWM outputs or external capture inputs available at pins.
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