Datasheet

P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
Direction
0:Input
1:Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
EN
Tomodule
1
0
Frommodule
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
1
0
DV
SS
DV
CC
P1REN.x
PadLogic
1
P1DS.x
0:Lowdrive
1:Highdrive
D
Frommodule
MSP430F532x
SLAS678D AUGUST 2010REVISED FEBRUARY 2013
www.ti.com
INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
70 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated