Datasheet

Unified
Clock
System
128KB
96KB
64KB
32KB
Flash
8KB+2KB
6KB+2KB
4KB+2KB
RAM
MCLK
ACLK
SMCLK
I/OPorts
P1/P2
2×8I/Os
Interrupt
&Wakeup
PA
1×16I/Os
CPUXV2
and
Working
Registers
EEM
(L:8+2)
XIN
XOUT
JTAG/
Interface
SBW
PA PB PC PD
DMA
3Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
PortMap
Control
(P4)
I/OPorts
P3/P4
2×8I/Os
PB
1×16I/Os
I/OPorts
P5/P6
2×8I/Os
PC
1×16I/Os
I/OPorts
P7/P8
1×8I/Os
1
PD
1×11I/Os
×3I/Os
PUPort
LDO
MPY32
TA0
Timer_A
5CC
Registers
TA1
Timer_A
3CC
Registers
TB0
Timer_B
7CC
Registers
RTC_A
CRC16
USCI0,1
USCI_Ax:
UART,
IrDA,SPI
USCI_Bx:
SPI,I2C
ADC12_A
200KSPS
16Channels
(14ext/2int)
Autoscan
12Bit
DVCC DVSS AVCC AVSS
P1.x P2.x
P3.x
P4.x
P5.x P6.x
PU.0,
PU.1
RST/NMI
TA2
Timer_A
3CC
Registers
REF
VCORE
MAB
MDB
P7.x P8.x
COMP_B
12Channels
LDOO LDOI
MSP430F532x
www.ti.com SLAS678D –AUGUST 2010–REVISED FEBRUARY 2013
Functional Block Diagram – MSP430F5329IPN, MSP430F5327IPN, MSP430F5325IPN
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