Datasheet

MSP430F532x

SLAS678D –AUGUST 2010–REVISED FEBRUARY 2013

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Peripheral File Map

Table 17. Peripherals

OFFSET ADDRESS

MODULE NAME BASE ADDRESS

RANGE

Special Functions (see Table 18) 0100h 000h-01Fh

PMM (see Table 19) 0120h 000h-010h

Flash Control (see Table 20) 0140h 000h-00Fh

CRC16 (see Table 21) 0150h 000h-007h

RAM Control (see Table 22) 0158h 000h-001h

Watchdog (see Table 23) 015Ch 000h-001h

UCS (see Table 24) 0160h 000h-01Fh

SYS (see Table 25) 0180h 000h-01Fh

Shared Reference (see Table 26) 01B0h 000h-001h

Port Mapping Control (see Table 27) 01C0h 000h-002h

Port Mapping Port P4 (see Table 27) 01E0h 000h-007h

Port P1/P2 (see Table 28) 0200h 000h-01Fh

Port P3/P4 (see Table 29) 0220h 000h-00Bh

Port P5/P6 (see Table 30) 0240h 000h-00Bh

Port P7/P8 (see Table 31) 0260h 000h-00Bh

Port PJ (see Table 32) 0320h 000h-01Fh

TA0 (see Table 33) 0340h 000h-02Eh

TA1 (see Table 34) 0380h 000h-02Eh

TB0 (see Table 35) 03C0h 000h-02Eh

TA2 (see Table 36) 0400h 000h-02Eh

Real-Time Clock (RTC_A) (see Table 37) 04A0h 000h-01Bh

32-Bit Hardware Multiplier (see Table 38) 04C0h 000h-02Fh

DMA General Control (see Table 39) 0500h 000h-00Fh

DMA Channel 0 (see Table 39) 0510h 000h-00Ah

DMA Channel 1 (see Table 39) 0520h 000h-00Ah

DMA Channel 2 (see Table 39) 0530h 000h-00Ah

USCI_A0 (see Table 40) 05C0h 000h-01Fh

USCI_B0 (see Table 41) 05E0h 000h-01Fh

USCI_A1 (see Table 42) 0600h 000h-01Fh

USCI_B1 (see Table 43) 0620h 000h-01Fh

ADC12_A (see Table 44) 0700h 000h-03Eh

Comparator_B (see Table 45) 08C0h 000h-00Fh

LDO-PWR and Port U configuration (see Table 46) 0900h 000h-014h