Datasheet

MSP430F5310, MSP430F5309
MSP430F5308, MSP430F5304
SLAS677E –SEPTEMBER 2010–REVISED NOVEMBER 2013 www.ti.com
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1)
, Figure 10 and Figure 11)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
1.8 V 11
PMMCOREV = 0 ns
3 V 8
t
STE,LEAD
STE lead time, STE low to clock
2.4 V 7
PMMCOREV = 3 ns
3 V 6
1.8 V 3
PMMCOREV = 0 ns
3 V 3
t
STE,LAG
STE lag time, Last clock to STE high
2.4 V 3
PMMCOREV = 3 ns
3 V 3
1.8 V 66
PMMCOREV = 0 ns
3 V 50
t
STE,ACC
STE access time, STE low to SOMI data out
2.4 V 36
PMMCOREV = 3 ns
3 V 30
1.8 V 30
PMMCOREV = 0 ns
3 V 23
STE disable time, STE high to SOMI high
t
STE,DIS
impedance
2.4 V 16
PMMCOREV = 3 ns
3 V 13
1.8 V 5
PMMCOREV = 0 ns
3 V 5
t
SU,SI
SIMO input data setup time
2.4 V 2
PMMCOREV = 3 ns
3 V 2
1.8 V 5
PMMCOREV = 0 ns
3 V 5
t
HD,SI
SIMO input data hold time
2.4 V 5
PMMCOREV = 3 ns
3 V 5
UCLK edge to SOMI valid, 1.8 V 76
C
L
= 20 pF ns
3 V 60
PMMCOREV = 0
t
VALID,SO
SOMI output data valid time
(2)
UCLK edge to SOMI valid, 2.4 V 44
C
L
= 20 pF ns
3 V 40
PMMCOREV = 3
1.8 V 18
C
L
= 20 pF
ns
PMMCOREV = 0
3 V 12
t
HD,SO
SOMI output data hold time
(3)
2.4 V 10
C
L
= 20 pF
ns
PMMCOREV = 3
3 V 8
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(USCI)
, t
SU,MI(Master)
+ t
VALID,SO(USCI)
).
For the master's parameters t
SU,MI(Master)
and t
VALID,MO(Master)
see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8 and Figure 9.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 8
and Figure 9.
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