Datasheet

Unified
Clock
System
32KB
24KB
16KB
Flash
6KB
RAM
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
EEM
(S:3+1)
XIN
XOUT
JTAG,
SBW
Interface
DMA
3 Channel
XT2IN
XT2OUT
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
PU Port
LDO
MPY32
TA0
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
USCI
A1: UART,
IrDA, SPI
B1: SPI, I2C
COMP_B
DVCC
DVSS
AVCC
AVSS
PU.0, PU.1
RST/NMI
TA2
Timer_A
3 CC
Registers
REF
VCORE
MAB
MDB
ADC10_A
200 KSPS
8 Channels
(6 ext, 2 int)
Window
Comparator
10 Bit
I/O Ports
P1, P2
1×8 I/Os
1
Interrupt,
Wakeup
PA
1×9 I/Os
×1 I/Os
PA PB PC
I/O Ports
P4
1
PB
1×8 I/Os
×8 I/Os
I/O Ports
P5, P6
1×6 I/Os
1
PC
1×10 I/Os
×4 I/Os
P1.x P2.x
P3.x
P4.x
P5.x P6.x
MSP430F5310, MSP430F5309
MSP430F5308, MSP430F5304
SLAS677E –SEPTEMBER 2010–REVISED NOVEMBER 2013 www.ti.com
Functional Block Diagram – MSP430F5310IRGZ, MSP430F5309IRGZ, MSP430F5308IRGZ,
MSP430F5310IPT, MSP430F5309IPT, MSP430F5308IPT
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Product Folder Links: MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304