Datasheet

MSP430F5310, MSP430F5309
MSP430F5308, MSP430F5304
www.ti.com SLAS677E –SEPTEMBER 2010–REVISED NOVEMBER 2013
Peripheral File Map
Table 16. Peripherals
OFFSET ADDRESS
MODULE NAME BASE ADDRESS
RANGE
Special Functions (see Table 17) 0100h 000h-01Fh
PMM (see Table 18) 0120h 000h-01Fh
Flash Control (see Table 19) 0140h 000h-00Fh
CRC16 (see Table 20) 0150h 000h-007h
RAM Control (see Table 21) 0158h 000h-001h
Watchdog (see Table 22) 015Ch 000h-001h
UCS (see Table 23) 0160h 000h-01Fh
SYS (see Table 24) 0180h 000h-01Fh
Shared Reference (see Table 25) 01B0h 000h-001h
Port Mapping Control (see Table 26) 01C0h 000h-002h
Port Mapping Port P4 (see Table 26) 01E0h 000h-007h
Port P1, P2 (see Table 27) 0200h 000h-01Fh
Port P3, P4 (see Table 28) 0220h 000h-00Bh
Port P5, P6 (see Table 29) 0240h 000h-00Bh
Port PJ (see Table 30) 0320h 000h-01Fh
TA0 (see Table 31) 0340h 000h-02Eh
TA1 (see Table 32) 0380h 000h-02Eh
TB0 (see Table 33) 03C0h 000h-02Eh
TA2 (see Table 34) 0400h 000h-02Eh
Real-Time Clock (RTC_A) (see Table 35) 04A0h 000h-01Bh
32-Bit Hardware Multiplier (see Table 36) 04C0h 000h-02Fh
DMA General Control (see Table 37) 0500h 000h-00Fh
DMA Channel 0 (see Table 37) 0510h 000h-00Ah
DMA Channel 1 (see Table 37) 0520h 000h-00Ah
DMA Channel 2 (see Table 37) 0530h 000h-00Ah
USCI_A0 (see Table 38) 05C0h 000h-01Fh
USCI_B0 (see Table 39) 05E0h 000h-01Fh
USCI_A1 (see Table 40) 0600h 000h-01Fh
USCI_B1 (see Table 41) 0620h 000h-01Fh
ADC10_A (see Table 42) 0740h 000h-01Fh
Comparator_B (see Table 43) 08C0h 000h-00Fh
LDO-PWR and Port U configuration (see Table 44) 0900h 000h-014h
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