Datasheet

MSP430F5310, MSP430F5309

MSP430F5308, MSP430F5304

SLAS677E –SEPTEMBER 2010–REVISED NOVEMBER 2013

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Table 9. Default Mapping

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

USCI_B1 SPI slave transmit enable (direction controlled by USCI)

P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK

USCI_A1 clock input/output (direction controlled by USCI)

USCI_B1 SPI slave in master out (direction controlled by USCI)

P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA

USCI_B1 I2C data (open drain and direction controlled by USCI)

USCI_B1 SPI slave out master in (direction controlled by USCI)

P4.2/P4MAP2 PM_UCB1SOMI/PM_UCB1SCL

USCI_B1 I2C clock (open drain and direction controlled by USCI)

USCI_A1 SPI slave transmit enable (direction controlled by USCI)

P4.3/P4MAP3 PM_UCB1CLK/PM_UCA1STE

USCI_B1 clock input/output (direction controlled by USCI)

USCI_A1 UART TXD (Direction controlled by USCI - output)

P4.4/P4MAP4 PM_UCA1TXD/PM_UCA1SIMO

USCI_A1 SPI slave in master out (direction controlled by USCI)

USCI_A1 UART RXD (Direction controlled by USCI - input)

P4.5/P4MAP5 PM_UCA1RXD/PM_UCA1SOMI

USCI_A1 SPI slave out master in (direction controlled by USCI)

P4.6/P4MAP6 PM_NONE None DVSS

P4.7/P4MAP7 PM_NONE None DVSS

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