Datasheet

MSP430F5310, MSP430F5309
MSP430F5308, MSP430F5304
SLAS677E –SEPTEMBER 2010–REVISED NOVEMBER 2013 www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
NO.
I/O
(1)
DESCRIPTION
NAME
RGZ,
RGC ZQE
PT
General-purpose digital I/O with reconfigurable port mapping secondary
P4.5/PM_UCA1RXD/ function
46 34 C9 I/O
PM_UCA1SOMI Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary
P4.6/PM_NONE 47 35 C8 I/O function
Default mapping: no secondary function.
General-purpose digital I/O with reconfigurable port mapping secondary
P4.7/PM_NONE 48 36 C7 I/O function
Default mapping: no secondary function.
B8,
VSSU 49 37 PU ground supply
B9
PU.0 50 38 A9 I/O General-purpose digital I/O - controlled by PU control register
NC 51 39 B7 I/O No connect.
PU.1 52 40 A8 I/O General-purpose digital I/O - controlled by PU control register
LDOI 53 41 A7 LDO input
LDOO 54 42 A6 LDO output
NC 55 43 B6 No connect.
AVSS2 56 44 A5 Analog ground supply
General-purpose digital I/O
P5.2/XT2IN 57 45 B5 I/O
Input terminal for crystal oscillator XT2
General-purpose digital I/O
P5.3/XT2OUT 58 46 B4 I/O
Output terminal of crystal oscillator XT2
Test mode pin – select digital I/O on JTAG pins
TEST/SBWTCK 59 47 A4 I
Spy-bi-wire input clock
General-purpose digital I/O
PJ.0/TDO 60 23 C5 I/O
Test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK 61 24 C4 I/O
Test data input or test clock input
General-purpose digital I/O
PJ.2/TMS 62 25 A3 I/O
Test mode select
General-purpose digital I/O
PJ.3/TCK 63 26 B3 I/O
Test clock
Reset input active low
(3)
RST/NMI/SBWTDIO 64 48 A2 I/O Non-maskable interrupt input
Spy-bi-wire data input/output
General-purpose digital I/O
P6.0/CB0/A0 1 1 A1 I/O Comparator_B input CB0 (not available on F5304 device)
Analog input A0 – ADC
General-purpose digital I/O
P6.1/CB1/A1 2 2 B2 I/O Comparator_B input CB1 (not available on F5304 device)
Analog input A1 – ADC
General-purpose digital I/O
P6.2/CB2/A2 3 3 B1 I/O Comparator_B input CB2 (not available on F5304 device)
Analog input A2 – ADC
General-purpose digital I/O
P6.3/CB3/A3 4 4 C2 I/O Comparator_B input CB3 (not available on F5304 device)
Analog input A3 – ADC
Reserved N/A N/A
(4)
Exposed thermal pad on QFN packages. Connection to V
SS
is recommended
Thermal Pad Pad Pad N/A
(not available on PT package devices).
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(4) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
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