Datasheet
MSP430F5310, MSP430F5309
MSP430F5308, MSP430F5304
www.ti.com
SLAS677E –SEPTEMBER 2010–REVISED NOVEMBER 2013
Table 2. Terminal Functions (continued)
TERMINAL
NO.
I/O
(1)
DESCRIPTION
NAME
RGZ,
RGC ZQE
PT
General-purpose digital I/O with port interrupt
P2.1/TA1.2 27 N/A G6 I/O
TA1 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P2.2/TA2CLK/SMCLK 28 N/A J6 I/O
TA2 clock signal TA2CLK input ; SMCLK output
General-purpose digital I/O with port interrupt
P2.3/TA2.0 29 N/A H6 I/O
TA2 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
P2.4/TA2.1 30 N/A J7 I/O
TA2 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt
P2.5/TA2.2 31 N/A J8 I/O
TA2 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P2.6/RTCCLK/DMAE0 32 N/A J9 I/O RTC clock output for calibration
DMA external trigger input
General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
P2.7/UCB0STE/UCA0CLK 33 N/A H7 I/O
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
General-purpose digital I/O
P3.0/UCB0SIMO/UCB0SDA 34 N/A H8 I/O Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
General-purpose digital I/O
P3.1/UCB0SOMI/UCB0SCL 35 N/A H9 I/O Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
P3.2/UCB0CLK/UCA0STE 36 N/A G8 I/O
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
General-purpose digital I/O
P3.3/UCA0TXD/UCA0SIMO 37 N/A G9 I/O Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
General-purpose digital I/O
P3.4/UCA0RXD/UCA0SOMI 38 N/A G7 I/O Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.0/PM_UCB1STE/
41 29 E8 I/O Default mapping: Slave transmit enable – USCI_B1 SPI mode
PM_UCA1CLK
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode
General-purpose digital I/O with reconfigurable port mapping secondary
P4.1/PM_UCB1SIMO/ function
42 30 E7 I/O
PM_UCB1SDA Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
General-purpose digital I/O with reconfigurable port mapping secondary
P4.2/PM_UCB1SOMI/ function
43 31 D9 I/O
PM_UCB1SCL Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.3/PM_UCB1CLK/
44 32 D8 I/O Default mapping: Clock signal input – USCI_B1 SPI slave mode
PM_UCA1STE
Default mapping: Clock signal output – USCI_B1 SPI master mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
DVSS2 39 27 F9 Digital ground supply
DVCC2 40 28 E9 Digital power supply
General-purpose digital I/O with reconfigurable port mapping secondary
P4.4/PM_UCA1TXD/ function
45 33 D7 I/O
PM_UCA1SIMO Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
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