Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com SLAS619J –AUGUST 2010–REVISED OCTOBER 2013
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 26 and
Figure 27)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
1.8 V 11
PMMCOREV = 0 ns
3 V 8
t
STE,LEAD
STE lead time, STE low to clock
2.4 V 7
PMMCOREV = 3 ns
3 V 6
1.8 V 3
PMMCOREV = 0 ns
3 V 3
t
STE,LAG
STE lag time, Last clock to STE high
2.4 V 3
PMMCOREV = 3 ns
3 V 3
1.8 V 66
PMMCOREV = 0 ns
3 V 50
t
STE,ACC
STE access time, STE low to SOMI data out
2.4 V 36
PMMCOREV = 3 ns
3 V 30
1.8 V 30
PMMCOREV = 0 ns
3 V 23
STE disable time, STE high to SOMI high
t
STE,DIS
impedance
2.4 V 16
PMMCOREV = 3 ns
3 V 13
1.8 V 5
PMMCOREV = 0 ns
3 V 5
t
SU,SI
SIMO input data setup time
2.4 V 2
PMMCOREV = 3 ns
3 V 2
1.8 V 5
PMMCOREV = 0 ns
3 V 5
t
HD,SI
SIMO input data hold time
2.4 V 5
PMMCOREV = 3 ns
3 V 5
1.8 V 76
UCLK edge to SOMI valid,
ns
C
L
= 20 pF, PMMCOREV = 0
3 V 60
t
VALID,SO
SOMI output data valid time
2.4 V 44
UCLK edge to SOMI valid,
ns
C
L
= 20 pF, PMMCOREV = 3
3 V 40
1.8 V 18
C
L
= 20 pF, PMMCOREV = 0 ns
3 V 12
t
HD,SO
SOMI output data hold time
2.4 V 10
C
L
= 20 pF, PMMCOREV = 3 ns
3 V 8
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 59
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131