Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com SLAS619J –AUGUST 2010–REVISED OCTOBER 2013
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24 and
Figure 25)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
SMCLK, ACLK
f
USCI
USCI input clock frequency f
SYSTEM
MHz
Duty cycle = 50% ± 10%
1.8 V 55
PMMCOREV = 0
3 V 38
t
SU,MI
SOMI input data setup time ns
2.4 V 30
PMMCOREV = 3
3 V 25
1.8 V 0
PMMCOREV = 0
3 V 0
t
HD,MI
SOMI input data hold time ns
2.4 V 0
PMMCOREV = 3
3 V 0
1.8 V 20
UCLK edge to SIMO valid,
C
L
= 20 pF, PMMCOREV = 0
3 V 18
t
VALID,MO
SIMO output data valid time ns
2.4 V 16
UCLK edge to SIMO valid,
C
L
= 20 pF, PMMCOREV = 3
3 V 15
1.8 V -10
C
L
= 20 pF, PMMCOREV = 0 ns
3 V -8
t
HD,MO
SIMO output data hold time
2.4 V -10
C
L
= 20 pF, PMMCOREV = 3 ns
3 V -8
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