Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619J –AUGUST 2010–REVISED OCTOBER 2013 www.ti.com
Outputs – Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
IO
MIN MAX UNIT
I
(OH5max)
= –1 mA
(2)
V
IO
– 0.25 V
IO
1.8 V
I
(OH5max)
= –3 mA
(3)
V
IO
– 0.60 V
IO
I
(OH5max)
= –2 mA
(2)
V
IO
– 0.25 V
IO
V
OH5
High-level output voltage 3 V V
I
(OH5max)
= –6 mA
(3)
V
IO
– 0.60 V
IO
I
(OH5max)
= –4 mA
(2)
V
IO
– 0.25 V
IO
5.0 V
I
(OL5max)
= -12 mA
(3)
V
IO
– 0.60 V
IO
I
(OL5max)
= 1 mA
(2)
V
SS
V
SS
+ 0.25
1.8 V
I
(OL5max)
= 3 mA
(3)
V
SS
V
SS
+ 0.60
I
(OL5max)
= 2 mA
(2)
V
SS
V
SS
+ 0.25
V
OL5
Low-level output voltage 3 V V
I
(OL5max)
= 6 mA
(3)
V
SS
V
SS
+ 0.60
I
(OH5max)
= 4 mA
(2)
V
SS
V
SS
+ 0.25
5.0 V
I
(OL5max)
= 12 mA
(3)
V
SS
V
SS
+ 0.60
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I
(OH5max)
and I
(OL5max)
, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
(3) The maximum total current, I
(OH5max)
and I
(OL5max)
, for all outputs combined, should not exceed ±200 mA to hold the maximum voltage
drop specified.
Output Frequency – Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
CC
= 1.8 V
16
PMMCOREVx = 0
Port output frequency PJ.0/SMCLK
f
Px.y
MHz
(with load) C
L
= 20 pF, R
L
= 1 kΩ
(1) (2)
V
CC
= 3 V
25
PMMCOREVx = 3
V
CC
= 1.8 V
PJ.3/ACLK
16
PMMCOREVx = 0
PJ.0/SMCLK
f
Port_CLK
Clock output frequency MHz
PJ.1/MCLK
V
CC
= 3 V
25
C
L
= 20 pF
(2)
PMMCOREVx = 3
(1) A resistive divider with 2 × 0.5 kΩ between V
CC
and V
SS
is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% V
CC
at the specified toggle frequency.
Output Frequency – Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
CC
= 1.8 V, V
IO
= 1.8 V
16
PMMCOREVx = 0
Port output frequency P1.6 port mapper SMCLK from P3.4 V
CC
= 3 V, V
IO
= 3 V
f
Px.y
25 MHz
(with load) C
L
= 20 pF, R
L
= 1 kΩ
(1) (2)
PMMCOREVx = 3
V
CC
= 3 V, V
IO
= 5 V
25
PMMCOREVx = 3
V
CC
= 1.8 V, V
IO
= 1.8V
16
PMMCOREVx = 0
P1.6 port mapper SMCLK from P3.4 V
CC
= 3 V, V
IO
= 3 V
f
Port_CLK
Clock output frequency 25 MHz
C
L
= 20 pF
(2)
PMMCOREVx = 3
V
CC
= 3 V, V
IO
= 5 V
25
PMMCOREVx = 3
(1) A resistive divider with 2 × 0.5 kΩ between V
CC
and V
SS
is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% V
CC
at the specified toggle frequency.
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