Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com SLAS619J –AUGUST 2010–REVISED OCTOBER 2013
Recommended Operating Conditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25°C (unless otherwise noted)
MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6 V
Supply voltage during program execution and flash
PMMCOREVx = 0, 1 2.0 3.6 V
V
CC
programming
PMMCOREVx = 0, 1, 2 2.2 3.6 V
V(AVCC) = V(DVCC) = V
CC
(1)(2)
PMMCOREVx = 0, 1, 2, 3 2.4 3.6 V
V
IO
Supply voltage of pins P1.6, P1.7, P2.0 to P2.7, P3.0, and P3.1 supplied by VIO
(3)
1.8 5.5 V
V
SS
Supply voltage V(AVSS) = V(DVSS) = V
SS
0 V
T
A
Operating free-air temperature –40 85 °C
T
J
Operating junction temperature –40 85 °C
C
(VCORE)
Recommended capacitor at VCORE
(4)
470 nF
C
(DVCC)
/
Capacitor ratio of DVCC to VCORE 10
C
(VCORE)
PMMCOREVx = 0,
1.8 V ≤ V
CC
≤ 3.6 V 0 12
(default condition)
PMMCOREVx = 1,
0 16
Processor frequency (maximum MCLK frequency)
(5) (6)
2.0 V ≤ V
CC
≤ 3.6 V
f
SYSTEM
MHz
(see Figure 2)
PMMCOREVx = 2,
0 20
2.2 V ≤ V
CC
≤ 3.6 V
PMMCOREVx = 3,
0 25
2.4 V ≤ V
CC
≤ 3.6 V
P
INT
Internal power dissipation V
CC
x I(DVCC) W
(V
CC
- V
IOH
) x I
IOH
+
P
IO
I/O power dissipation of the I/O pins powered by DVCC W
V
IOL
x I
IOL
(V
IO
- V
IOH5
) x I
IOH5
+
P
IO5
I/O power dissipation of the I/O pins powered by VIO W
V
IOL5
x I
IOL5
P
MAX
Maximum allowed power dissipation, P
MAX
> P
IO
+ P
IO5
+ P
INT
(T
J
- T
A
)/θ
JA
W
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC)
can be tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(3) It is recommended to power DVCC and AVCC prior to DVIO. At DVCC and AVCC voltages higher than 1.8 V, the maximum difference
of 0.3 V between DVIO and DVCC and AVCC can be exceeded.
(4) A capacitor tolerance of ±20% or better is required.
(5) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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