Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com SLAS619J –AUGUST 2010–REVISED OCTOBER 2013
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6. Interrupt Sources, Flags, and Vectors
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up
External Reset WDTIFG, KEYV (SYSRSTIV)
(1) (2)
Reset 0FFFEh 63, highest
Watchdog Timeout, Key Violation
Flash Memory Key Violation
System NMI
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access
JMBOUTIFG (SYSSNIV)
(1)
JTAG Mailbox
User NMI
NMI
NMIIFG, OFIFG, ACCVIFG (SYSUNIV)
(1) (2)
(Non)maskable 0FFFAh 61
Oscillator Fault
Flash Memory Access Violation
Comp_B CBIIFG, CBIFG (CBIV)
(1) (3)
Maskable 0FFF8h 60
TEC0FLTIFG, TEC0EXCLRIFG,
TEC0 Maskable 0FFF6h 59
TEC0AXCLRIFG
(1) (3)
TD0 TD0CCR0 CCIFG0
(3)
Maskable 0FFF4h 58
TD0CCR1 CCIFG1, ... TD0CCR2 CCIFG2,
TD0 TD0IFG, TD0HFLIFG, TD0HFHIFG, TD0HLKIFG, Maskable 0FFF2h 57
TD0HUNLKIFG (TD0IV)
(1) (3)
Watchdog Timer_A Interval
WDTIFG Maskable 0FFF0h 56
Timer Mode
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)
(1) (3)
Maskable 0FFEEh 55
UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt
USCI_B0 Receive or Transmit Maskable 0FFECh 54
Flags (UCB0IV)
(1) (3)
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10_A (MSP430F51x2 only) ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG Maskable 0FFEAh 53
(ADC10IV)
(1) (3)
TA0 TA0CCR0 CCIFG0
(3)
Maskable 0FFE8h 52
TA0CCR1 CCIFG1 ... TA0CCR2 CCIFG2,
TA0 Maskable 0FFE6h 51
TA0IFG (TA0IV)
(1) (3)
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)
(1) (3)
Maskable 0FFE4h 50
TEC1FLTIFG, TEC1EXCLRIFG,
TEC1 Maskable 0FFE2 49
TEC1AXCLRIFG
(1) (3)
TD1 TD1CCR0 CCIFG0
(3)
Maskable 0FFE0h 48
TD1CCR1 CCIFG1 ... TD1CCR2 CCIFG2,
TD1 TD1IFG, TD1HFLIFG, TD1HFHIFG, TD1HLKIFG, Maskable 0FFDEh 47
TD1HUNLKIFG (TD1IV)
(1) (3)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)
(1) (3)
Maskable 0FFDCh 46
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)
(1) (3)
Maskable 0FFDAh 45
0FFD8h 44
Reserved Reserved
(4)
⋮ ⋮
0FF80h 0, lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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