Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619J –AUGUST 2010–REVISED OCTOBER 2013 www.ti.com
Table 3. Terminal Functions (continued)
TERMINAL
NO. I/O
(1)
DESCRIPTION
NAME
RSB DA YFF
P2.1/ I/O, General-purpose digital I/O
14 18 B7
PM_TD1.0 DV
IO
TD1 CCR0 compare output/capture input
P2.2/ I/O, General-purpose digital I/O
15 19 C7
PM_TD1.1 DV
IO
TD1 CCR1 compare output/capture input
P2.3/ I/O, General-purpose digital I/O
16 20 D5
PM_TD1.2 DV
IO
TD1 CCR2 compare output/capture input
DVIO 17 21 D7 5V tolerant digital I/O power supply
DVSS 18 22 E7 Digital ground supply
P2.4/ General-purpose digital I/O
PM_TEC0CLR/ I/O, TD0 external clear input/TD0 fault input channel 2 (controlled by module input enable)
19 23 D6
PM_TEC0FLT2/ DV
IO
<br/>
PM_TD0.0 TD0 CCR0 compare output
P2.5/ General-purpose digital I/O
I/O,
PM_TEC0FLT0/ 20 24 F7 TD0 fault input channel 0
DV
IO
PM_TD0.1 TD0 CCR1 compare output
P2.6/ General-purpose digital I/O
I/O,
PM_TEC0FLT1/ 21 25 E6 TD0 fault input channel 1
DV
IO
PM_TD0.2 TD0 CCR2 compare output
P2.7/ General-purpose digital I/O
PM_TEC1CLR/ I/O, TD1 external clear/TD1 fault input channel 1 (controlled by module input enable)
22 26 E5
PM_TEC1FLT1/ DV
IO
<br/>
PM_TD1.0 TD1 CCR0 compare output
P3.0/ General-purpose digital I/O
I/O,
PM_TEC1FLT2 / 23 27 F6 TD1 fault input channel 2
DV
IO
PM_TD1.1 TD1 CCR1 compare output
P3.1/ General-purpose digital I/O
I/O,
PM_TEC1FLT0/ 24 28 F5 TD1 fault input channel 0
DV
IO
PM_TD1.2 TD1 CCR2 compare output
VCORE 25 29 F4 Regulated core power supply
DVSS 26 30 F3 Digital ground supply
DVCC 27 31 F2 Digital power supply
PJ.6/ General-purpose digital I/O
TD1CLK/ TD1 clock input
28 32 E3 I/O
TD0.1/ TD0 CCR1 compare output
CB15 Comparator_B Input 15
P3.2/ General-purpose digital I/O
PM_TD0.0/ TD0 CCR0 capture input
29 33 E2 I/O
PM_SMCLK/ SMCLK output
CB14 Comparator_B Input 14
P3.3/ General-purpose digital I/O
PM_TA0CLK/ TA0 clock input
30 34 F1 I/O
PM_CBOUT/ Comparator_B output
CB13 Comparator_B Input 13
P3.4/ General-purpose digital I/O
PM_TD0CLK/ 31 - E1 I/O TD0 clock input
PM_MCLK MCLK output
TEST/ Test mode pin – select digital I/O on JTAG pins
32 35 E4
SBWTCK Spy-Bi-Wire input clock
RST/ Reset input active low
(3)
NMI/ 33 36 D2 Non-maskable interrupt input
SBWTDIO Spy-By-Wire data input/output
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
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