Datasheet

MSP430F5172, MSP430F5152, MSP430F5132

MSP430F5171, MSP430F5151, MSP430F5131

SLAS619J –AUGUST 2010–REVISED OCTOBER 2013

www.ti.com

Table 48. Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P2.x) x FUNCTION

P2DIR.x P2SEL.x P2MAP.x

P2.0/ 0 P2.x (I/O) I: 0; O: 1 0 X

PM_TD0.2 TD0.CCI2A 0 1 default

TD0.TA2 1 1 default

P2.1/ 1 P2.x (I/O) I: 0; O: 1 0 X

PM_TD1.0 TD1.CCI0A 0 1 default

TD1.TA0 1 1 default

P2.2/ 2 P2.x (I/O) I: 0; O: 1 0 X

PM_TD1.1 TD1.CCI1A 0 1 default

TD1.TA1 1 1 default

P2.3/ 3 P2.x (I/O) I: 0; O: 1 0 0

PM_TD1.2 TD1.CCI2A 0 1 default

TD1.TA2 1 1 default

P2.4/ 4 P2.x (I/O) I: 0; O: 1 0 X

PM_TEC0CLR/ TD0.TECEXTCLR, controlled by enable signals in the TEC0 module 0 1 default

PM_TEC0FLT2/ TD0.TECXFLT2, controlled by enable signals in the TEC0 module 0 1 default

PM_TD0.0 TD0.TA0 1 1 default

P2.5/ 5 P2.x (I/O) I: 0; O: 1 0 x

PM_TEC0FLT0/ TD0.TECXFLT0, controlled by enable signals in the TEC0 module 0 1 default

PM_TD0.1 TD0.TA1 1 1 default

P2.6/ 6 P2.x (I/O) I: 0; O: 1 0 X

PM_TEC0FLT1/ TD0.TECXFLT1, controlled by enable signals in the TEC0 module 0 1 default

PM_TD0.2 TD0.TA2 1 1 default

P2.7/ 7 P2.x (I/O) I: 0; O: 1 0 X

PM_TEC1CLR/ TD1.TECEXTCLR, controlled by enable signals in the TEC1 module 0 1 default

PM_TEC1FLT1/ TD1.TECXFLT1, controlled by enable signals in the TEC1 module 0 1 default

PM_TD1.0 TD1.TA0 1 1 default

Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131