Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com SLAS619J –AUGUST 2010–REVISED OCTOBER 2013
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
DV
CC(PGM/ERASE)
Program and erase supply voltage 1.8 3.6 V
I
PGM
Supply current from DVCC during program 3 5 mA
I
ERASE
Supply current from DVCC during erase 2 6.5 mA
I
MERASE
, I
BANK
Supply current from DVCC during mass erase or bank erase 2 6.5 mA
t
CPT
Cumulative program time See
(1)
16 ms
Program and erase endurance 10
4
10
5
cycles
t
Retention
Data retention duration T
J
= 25°C 100 years
t
Word
Word or byte program time See
(2)
64 85 µs
t
Block, 0
Block program time for first byte or word See
(2)
49 65 µs
Block program time for each additional byte or word, except for last
t
Block, 1–(N–1)
See
(2)
37 49 µs
byte or word
t
Block, N
Block program time for last byte or word See
(2)
55 73 µs
t
Mass Erase
Mass erase time See
(2)
23 32 ms
t
Seg Erase
Segment erase time See
(2)
23 32 ms
MCLK frequency in marginal read mode (FCLK4.MGR0 = 1 or
f
MCLK,MGR
0 1 MHz
FCTL4.MGR1 = 1)
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER V
CC
MIN TYP MAX UNIT
f
SBW
Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
t
SBW,Low
Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs
t
SBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
(1)
2.2 V, 3 V 1 µs
t
SBW,Rst
Spy-Bi-Wire return to normal operation time 15 100 µs
2.2 V 0 5 MHz
f
TCK
TCK input frequency, 4-wire JTAG
(2)
3 V 0 10 MHz
R
internal
Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the minimum t
SBW,En
time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) f
TCK
may be restricted to meet the timing requirements of the module selected.
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