Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com SLAS619J –AUGUST 2010–REVISED OCTOBER 2013
10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1.4 V ≤ (VEREF+ – VEREF-)min ≤ 1.6 V ±1.0
E
I
Integral linearity error LSB
1.6 V < (VEREF+ – VEREF-)min ≤ V
AVCC
±1.0
(VEREF+ – VEREF-)min ≤ (VEREF+ – VEREF-),
E
D
Differential linearity error ±1.0 LSB
C
VEREF+
= 20 pF
(VEREF+ – VEREF-)min ≤ (VEREF+ – VEREF-),
E
O
Offset error Internal impedance of source R
S
< 100 Ω, ±1.0 LSB
C
VEREF+
= 20 pF
Gain error, external reference ±1.0 LSB
(VEREF+ – VEREF-)min ≤ (VEREF+ – VEREF-),
C
VEREF+
= 20 pF
E
G
Gain error, external reference, buffered ±1.5 LSB
Gain error, internal reference See
(1)
±1.5% VREF
Total unadjusted error, external buffered (VEREF+ – VEREF-)min ≤ (VEREF+ – VEREF-),
±1.0 ±2.0 LSB
and unbuffered reference C
VEREF+
= 20 pF
E
T
Total unadjusted error, internal reference See
(1)
±1.5% VREF
(1) Dominated by the absolute voltage of the integrated reference voltage.
REF, External Reference (MSP430F51x2 Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Positive external reference
VEREF+ VEREF+ > VEREF-
(2)
1.4 AV
CC
V
voltage input
Negative external reference
VEREF- VEREF+ > VEREF-
(3)
0 1.2 V
voltage input
VEREF+ – Differential external
VEREF+ > VEREF-
(4)
1.4 AV
CC
V
VEREF- reference voltage input
1.4 V ≤ VEREF+ ≤ V(AVCC), VEREF- = 0 V,
f
ADC10CLK
= 5 MHz, ADC10SHTx = 0x0001, 2.2 V, 3 V ±8.5 ±26 µA
Conversion rate 200 ksps
I
(VEREF+)
Static input current
I
(VEREF-)
1.4 V ≤ VEREF+ ≤ V(AVCC), VEREF- = 0 V,
f
ADC10CLK
= 5 MHZ, ADC10SHTX = 0x1000, 2.2 V, 3 V ±1 µA
Conversion rate 20 ksps
Capacitance at VEREF+
C
(VEREF+/-)
See
(5)
10 µF
and VEREF- terminals
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C
I
, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VEREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
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