Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com SLAS619J –AUGUST 2010–REVISED OCTOBER 2013
Table 38. USCI0_A Registers (Base Address: 05C0h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI control 0 UCA0CTL0 01h
USCI control 1 UCA0CTL1 00h
USCI baud rate 0 UCA0BR0 06h
USCI baud rate 1 UCA0BR1 07h
USCI modulation control UCA0MCTL 08h
USCI status UCA0STAT 0Ah
USCI receive buffer UCA0RXBUF 0Ch
USCI transmit buffer UCA0TXBUF 0Eh
USCI LIN control UCA0ABCTL 10h
USCI IrDA transmit control UCA0IRTCTL 12h
USCI IrDA receive control UCA0IRRCTL 13h
USCI interrupt enable UCA0IE 1Ch
USCI interrupt flags UCA0IFG 1Dh
USCI interrupt vector word UCA0IV 1Eh
Table 39. USCI0_B Registers (Base Address: 05E0h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 0 UCB0CTL0 00h
USCI synchronous control 1 UCB0CTL1 01h
USCI synchronous bit rate 0 UCB0BR0 06h
USCI synchronous bit rate 1 UCB0BR1 07h
USCI synchronous status UCB0STAT 0Ah
USCI synchronous receive buffer UCB0RXBUF 0Ch
USCI synchronous transmit buffer UCB0TXBUF 0Eh
USCI I2C own address UCB0I2COA 10h
USCI I2C slave address UCB0I2CSA 12h
USCI interrupt enable UCB0IE 1Ch
USCI interrupt flags UCB0IFG 1Dh
USCI interrupt vector word UCB0IV 1Eh
Table 40. ADC10_A Registers (MSP430F51x2 Devices Only) (Base Address: 0740h)
REGISTER DESCRIPTION REGISTER OFFSET
ADC10_A Control register 0 ADC10CTL0 00h
ADC10_A Control register 1 ADC10CTL1 02h
ADC10_A Control register 2 ADC10CTL2 04h
ADC10_A Window Comparator Low Threshold ADC10LO 06h
ADC10_A Window Comparator High Threshold ADC10HI 08h
ADC10_A Memory Control Register 0 ADC10MCTL0 0Ah
ADC10_A Conversion Memory Register ADC10MEM0 12h
ADC10_A Interrupt Enable ADC10IE 1Ah
ADC10_A Interrupt Flags ADC10IGH 1Ch
ADC10_A Interrupt Vector Word ADC10IV 1Eh
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