Datasheet
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619J –AUGUST 2010–REVISED OCTOBER 2013
www.ti.com
DESCRIPTION
The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows the devices to wake up from low-power modes to active mode in
less than 5 µs.
The MSP430F51x2 series are microcontroller configurations with two 16-bit high-resolution timers, universal
serial communication interfaces (USCI_A0 and USCI_B0), a 32-bit hardware multiplier, a high-performance 10-bit
analog-to-digital converter (ADC), an on-chip comparator, a three-channel DMA, 5-V tolerant I/Os, and up to
29 I/O pins.
The MSP430F51x1 series are microcontroller configurations with two 16-bit high-resolution timers, universal
serial communication interfaces (USCI_A0 and USCI_B0), a 32-bit hardware multiplier, an on-chip comparator, a
three-channel DMA, 5-V tolerant I/Os, and up to 29 I/O pins.
Typical applications for these devices include analog and digital sensor systems, LED lighting, digital power
supply, motor control, remote controls, thermostats, digital timers, and hand-held meters
Table 1 summarizes the available family members.
Table 1. Family Members
(1)(2)
USCI
Flash SRAM ADC10_A Comp_B
Channel A: Channel B:
Device Timer_A
(3)
Timer_D
(4)
I/O Package
(KB) (KB) (Ch) (Ch)
UART, IrDA,
SPI, I
2
C
SPI
40 QFN
9 ext, 2 int 16 31
MSP430F5172 32 2 3 3, 3 1 1 40 DSBGA
(5)
8 ext, 2 int 15 29 38 TSSOP
40 QFN
9 ext, 2 int 16 31
MSP430F5152 16 2 3 3, 3 1 1 40 DSBGA
(5)
8 ext, 2 int 15 29 38 TSSOP
40 QFN
9 ext, 2 int 16 31
MSP430F5132 8 1 3 3, 3 1 1 40 DSBGA
(5)
8 ext, 2 int 15 29 38 TSSOP
40 QFN
16 31
MSP430F5171 32 2 3 3, 3 1 1 - 40 DSBGA
(5)
15 29 38 TSSOP
40 QFN
16 31
MSP430F5151 16 2 3 3, 3 1 1 - 40 DSBGA
(5)
15 29 38 TSSOP
40 QFN
16 31
MSP430F5131 8 1 3 3, 3 1 1 - 40 DSBGA
(5)
15 29 38 TSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_D with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_D, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) Product Preview
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