Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com SLAS619J –AUGUST 2010–REVISED OCTOBER 2013
Table 9. Default Mapping
PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
P1.0/PM_UCA0CLK/ PM_UCA0CLK USCI_A0 clock input/output USCI_B0 SPI slave transmit enable
PM_UCB0STE/A0/CB0 PM_UCB0STE (direction controlled by USCI) (direction controlled by USCI)
P1.1/PM_UCA0TXD/ PM_UCA0TXD USCI_A0 UART TXD (Direction USCI_A0 SPI slave in master out
PM_UCA0SIMO/A1/CB1 PM_UCA0SIMO controlled by USCI - output) (direction controlled by USCI)
P1.2/PM_UCA0RXD/ PM_UCA0RXD USCI_A0 UART RXD (Direction USCI_A0 SPI slave out master in
PM_UCA0SOMI/A2/CB2 PM_UCA0SOMI controlled by USCI - input) (direction controlled by USCI)
P1.3/PM_UCB0CLK/ PM_UCB0CLK USCI_B0 clock input/output USCI_A0 SPI slave transmit enable
PM_UCA0STE/A3/CB3 PM_UCA0STE (direction controlled by USCI) (direction controlled by USCI)
P1.4/PM_UCB0SIMO/ PM_UCB0SIMO USCI_B0 SPI slave in master out USCI_B0 I2C data (open drain and
PM_UCB0SDA/A4/CB4 PM_UCB0SDA (direction controlled by USCI) direction controlled by USCI)
P1.5/PM_UCB0SOMI/ PM_UCB0SOMI USCI_B0 SPI slave out master in USCI_B0 I2C clock (open drain and
PM_UCB0SCL/A5/CB5 PM_UCB0SCL (direction controlled by USCI) direction controlled by USCI)
P1.6/PM_TD0.0 PM_TD0.0 TD0 input capture channel 0 TD0 output compare channel 0
P1.7/PM_TD0.1 PM_TD0.1 TD0 input capture channel 1 TD0 output compare channel 1
P2.0/PM_TD0.2 PM_TD0.2 TD0 input capture channel 2 TD0 output compare channel 2
P2.1/PM_TD1.0 PM_TD1.0 TD1 input capture channel 0 TD1 output compare channel 0
P2.2/PM_TD1.1 PM_TD1.1 TD1 input capture channel 1 TD1 output compare channel 1
P2.3/PM_TD1.2 PM_TD1.2 TD1 input capture channel 2 TD1 output compare channel 2
TD0 external clear input (controlled
P2.4/PM_TEC0CLR/ PM_CLR1TD0.0 by module input enable)
TD0 output compare channel 0
PM_TEC0FLT2/PM_TD0.0 PM_FLT1_2TD0.0 TD0 fault input channel 2
(controlled by module input enable)
P2.5/PM_TEC0FLT0/PM_TD0.1 PM_FLT1_0TD0.1 TD0 fault input channel 0 TD0 output compare channel 1
P2.6/PM_TEC0FLT1/PM_TD0.2 PM_FLT1_1TD0.2 TD0 fault input channel 1 TD0 output compare channel 2
TD1 external clear input (controlled
P2.7/PM_TEC1CLR/ PM_CLR2TD1.0 by module input enable)
TD1 output compare channel 0
PM_TEC1FLT1/PM_TD1.0 PM_FLT2_1TD1.0 TD1 fault input channel 1
(controlled by module input enable)
P3.0/PM_TEC1FLT2/
PM_FLT2_2TD1.1 TD1 fault input channel 2 TD1 output compare channel 1
PM_TD1.1
P3.1/PM_TEC1FLT0/
PM_FLT2_0TD1.2 TD1 fault input channel 0 TD1 output compare channel 2
PM_TD1.2
P3.2/PM_TD0.0/
PM_TD0.0SMCLK TD0 input capture channel 0 SMCLK output
PM_SMCLK/CB14
P3.3/PM_TA0CLK/
PM_TA0CLKCBOUT TA0 input clock Comparator_B output
PM_CBOUT/CB13
P3.4/PM_TD0CLK/
PM_TD0CLKMCLK TD0 input clock MCLK output
PM_MCLK
P3.5/PM_TA0.2/
PM_TA3_2 TA0 input capture channel 0 TA0 output compare channel 0
VEREF+/CB12
P3.6/PM_TA0.1/A7
PM_TA3_1 TA0 input capture channel 1 TA0 output compare channel 1
VEREF-/CB11
P3.7/PM_TA0.0/
PM_TA3_0 TA0 input capture channel 2 TA0 output compare channel 2
A6/CB10
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131