Datasheet

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619K –AUGUST 2010–REVISED JANUARY 2014 www.ti.com
Timer_D, Input Capture and Output Compare Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Timer_D input capture timing, minimum pulse duration to
t
TD,cap
f
MAX
= 262 MHz 4 ns
trigger input capture event
Timer0_D input capture timing, matching between input
f
MAX
= 262 MHz 1 2 LSB
capture channels P1.6 to P1.7 and P2.0
t
TD0,cap,matching
Timer0_D input capture timing, matching between input
f
MAX
= 262 MHz 3 4 LSB
capture channels. P2.4 to P2.5 and P2.6
Timer1_D input capture timing, matching between input
f
MAX
= 262 MHz 2 3 LSB
capture channels P2.1 to P2.2 and P2.3
t
TD1,cap,matching
Timer1_D input capture timing, matching between input
f
MAX
= 262 MHz 2 4 LSB
capture channels. P2.7 to P3.0 and P3.1
Timer0_D and Timer1_D input capture timing, matching
t
TD01,cap,matching
between input capture channels. Timer0_D is the high- f
MAX
= 262 MHz 4 8 LSB
resolution clock generator source.
Rising edges,
4 ns
f
MAX
= 262 MHz
Timer0_D output compare timing, matching between
Falling edges,
t
TD0,comp,matching
output capture compare channels for pins P1.6, P1.7, and 4 ns
f
MAX
= 262 MHz
P2.0
Rising and falling edges,
8 ns
f
MAX
= 262 MHz
Rising edges,
4 ns
f
MAX
= 262 MHz
Timer1_D output compare timing, matching between
Falling edges,
t
TD1,comp,matching
output capture compare channels for pins P2.1, P2.2, and 4 ns
f
MAX
= 262 MHz
P2.3
Rising and falling edges,
8 ns
f
MAX
= 262 MHz
Timer0_D and Timer1_D output compare timing, matching
All edges,
t
TD01,comp,matching
between output compare channels. Timer0_D is the high- 8 LSB
f
MAX
= 262 MHz
resolution clock generator source.
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