Datasheet

Unified
Clock
System
32KB
16KB
8KB
Flash
2KB
2KB
1KB
RAM
MCLK
ACLK
SMCLK
I/O Ports
P1
8 I/Os
2x 5V 20mA
Interrupt
and Wakeup
Pullup/down
Resistors
CPUXV2
and
Working
Registers
EEM
(S: 3+1)
XIN XOUT
JTAG/
SBW
Interface
3 DMA
Channel
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port
Mapping
Controller
MPY32
TA0
Timer_A
3 CC
Registers
USCI
A0: UART,
IrDA, SPI
B0: SPI, I2C
DVCC
DVSS
AVSS
P1.x
8
RST/NMI
COMP_B
16 Channels
High,
Medium, and
Ultralow
Power
Modes
REF
Voltage
Reference
DVSS
I/O Ports
P2
8 I/Os
8x 5V 20mA
Interrupt
and Wakeup
Pullup/down
Resistors
P2.x
8
I/O Ports
P3
8 I/Os
2x 5V 20mA
Pullup/down
Resistors
P3.x
8
I/O Ports
PJ
7 I/Os
Pullup/down
Resistors
PJ.x
7
CRC16
TD1
Timer_D
256 MHz
3 CC
Registers
With Buffer
EventControl
≤
TD0
Timer_D
256 MHz
3 CC
Registers
With Buffer
EventControl
≤
DVIOAVCC
32KB
16KB
8KB
Flash
2KB
2KB
1KB
RAM
MCLK
ACLK
SMCLK
I/O Ports
P1
8 I/Os
2x 5V 20mA
Interrupt
and Wakeup
Pullup/down
Resistors
CPUXV2
and
Working
Registers
EEM
(S: 3+1)
XIN XOUT
JTAG/
SBW
Interface
3 DMA
Channel
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port
Mapping
Controller
MPY32
TA0
Timer_A
3 CC
Registers
USCI
A0: UART,
IrDA, SPI
B0: SPI, I2C
ADC10_A
200 KSPS
9 Channels
10 Bit
DVCC
DVSS
AVSS
P1.x
8
RST/NMI
COMP_B
16 Channels
High,
Medium, and
Ultralow
Power
Modes
REF
Voltage
Reference
DVSS
I/O Ports
P2
8 I/Os
8x 5V 20mA
Interrupt
and Wakeup
Pullup/down
Resistors
P2.x
8
I/O Ports
P3
8 I/Os
2x 5V 20mA
Pullup/down
Resistors
P3.x
8
I/O Ports
PJ
7 I/Os
Pullup/down
Resistors
PJ.x
7
CRC16
TD1
Timer_D
256 MHz
3 CC
Registers
With Buffer
EventControl
≤
TD0
Timer_D
256 MHz
3 CC
Registers
With Buffer
EventControl
≤
DVIOAVCC
Unified
Clock
System
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com SLAS619K –AUGUST 2010–REVISED JANUARY 2014
Functional Block Diagram, MSP430F51x2
Functional Block Diagram, MSP430F51x1
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