Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 16-Bit 8 MHz I/O number 48

MSP430F47x

MIXED SIGNAL MICROCONTROLLER

SLAS629A -- MARCH 2009 -- REVISED APRIL 2009

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU goes

into LPM4 immediately after power--up.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT

WORD

ADDRESS

PRIORITY

Power-Up

External Reset

Watchdog

Flash Memory

PC Out--of--Range (see Note 4)

PORIFG

RSTIFG

WDTIFG

KEYV

(see Note 1)

Reset 0xFFFE 15, highest

NMI

Oscillator Fault

Flash Memory Access Violation

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1, 2 and 4)

(Non)maskable

0xFFFC 14

Timer_B3 TBCCR0 CCIFG0 (see Note 2) Maskable 0xFFFA 13

Timer_B3

TBCCR1 CCIFG1 ... TBCCR3 CCIFG3,

TBIFG (see Notes 1 and 2)

Maskable 0xFFF8 12

Comparator_A CAIFG Maskable 0xFFF6 11

Watchdog Timer+ WDTIFG Maskable 0xFFF4 10

USCI_A0/USCI_B0 receive

USCI_B0 I2C status

UCA0RXIFG, UCB0RXIFG

(see Notes 1 and 5)

Maskable 0xFFF2 9

USCI_A0/USCI_B0 transmit

USCI_B0 I2C receive/transmit

UCA0TXIFG, UCB0TXIFG

(see Note 1 and 6)

Maskable 0xFFF0 8

SD16_A SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG

(see Notes 1 and 2)

Maskable 0xFFEE 7

Timer_A3 TACCR0CCIFG0(seeNote2) Maskable 0xFFEC 6

Timer_A3

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG (see Notes 1 and 2)

Maskable 0xFFEA 5

I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0xFFE8 4

DAC12 DAC12_0IFG, DAC12_1IFG Maskable 0xFFE6 3

Maskable 0xFFE4 2

I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0xFFE2 1

Basic Timer1/RTC BTIFG Maskable 0xFFE0 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.

3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

4. Access and key violations, KEYV and ACCVIFG.

5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.

6. In UAR T/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.